From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 18:28:50 +0000 (-0700)
Subject: Fix CARRY4 abc_box_id
X-Git-Tag: working-ls180~1208^2~44
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf020befeb99df2296f2efe722410e49becb44dd;p=yosys.git

Fix CARRY4 abc_box_id
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 94bc3ef86..3937d3536 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *)
+(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];