From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 30 Sep 2018 03:25:28 +0000 (+0100)
Subject: yuk. break id_regs.py being a generic tool by skipping csr ops
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf0a17cc42b48fb0d2d2fd8ab173f1c30e913cfc;p=riscv-isa-sim.git

yuk. break id_regs.py being a generic tool by skipping csr ops

trying to use c preprocessor macros to skip CSRs in sv from being
parallelised is too painful, and is necessary to do.  a parallel CSR
read/write does not make sense
---

diff --git a/id_regs.py b/id_regs.py
index 6b8a678..0a99004 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -52,7 +52,12 @@ allfloats = floatpatterns + cfloatpatterns
 floatmask = (1<<len(allfloats)-1)
 allints = intpatterns + cintpatterns[2:]
 
+skip = '#define USING_NOREGS\n' \
+       '#define REGS_PATTERN 0x0\n'
 def find_registers(fname):
+    # HACK! macro-skipping csr* instructions too painful
+    if 'csr' in fname:
+        return skip
     res = []
     isintfloat = 0x0 + floatmask << len(allints)
     with open(fname) as f:
@@ -88,8 +93,7 @@ def find_registers(fname):
                 isintfloat &= ~(1 << (idx+len(allints)))
             res.append('#define USING_REG_%s' % p)
     if not res:
-        return '#define USING_NOREGS\n' \
-               '#define REGS_PATTERN 0x0\n'
+        return skip
     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
     return '\n'.join(res)