From: Uros Bizjak Date: Wed, 15 Apr 2015 19:32:07 +0000 (+0200) Subject: i386.md (*cmpi_mixed): Merge with *cmpi_mixed): Merge with *cmpi_sse using enabled attribute. * config/i386/i386.md (*cmpi_mixed): Merge with *cmpi_sse using enabled attribute. (*extendsfdf2_mixed): Merge with *extendsfdf2_sse using enabled attribute. (*truncdfsf_fast_mixed): Merge with *truncdfsf_fast_sse using enabled attribute. (*float2_mixed): Rename from *float2_sse. (*absneg2_mixed): Merge with *absneg2_sse using enabled attribute. (*fop__comm_mixed): Merge with *fop__comm_sse using enabled attribute. From-SVN: r222131 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index afa9266d1f8..6571c1f1558 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-04-15 Uros Bizjak + + * config/i386/i386.md (*cmpi_mixed): + Merge with *cmpi_sse using enabled attribute. + (*extendsfdf2_mixed): Merge with *extendsfdf2_sse using enabled + attribute. + (*truncdfsf_fast_mixed): Merge with *truncdfsf_fast_sse using + enabled attribute. + (*float2_mixed): Rename from + *float2_sse. + (*absneg2_mixed): Merge with *absneg2_sse using + enabled attribute. + (*fop__comm_mixed): Merge with *fop__comm_sse using + enabled attribute. + 2015-04-15 Tom de Vries PR other/65487 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 7195882f03d..922b2b2d38c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1641,19 +1641,15 @@ (compare:FPCMP (match_operand:MODEF 0 "register_operand" "f,x") (match_operand:MODEF 1 "nonimmediate_operand" "f,xm")))] - "TARGET_MIX_SSE_I387 - && SSE_FLOAT_MODE_P (mode)" + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" "* return output_fp_compare (insn, operands, true, mode == CCFPUmode);" [(set_attr "type" "fcmp,ssecomi") (set_attr "prefix" "orig,maybe_vex") (set_attr "mode" "") - (set (attr "prefix_rep") - (if_then_else (eq_attr "type" "ssecomi") - (const_string "0") - (const_string "*"))) + (set_attr "prefix_rep" "*,0") (set (attr "prefix_data16") - (cond [(eq_attr "type" "fcmp") + (cond [(eq_attr "alternative" "0") (const_string "*") (eq_attr "mode" "DF") (const_string "1") @@ -1661,28 +1657,12 @@ (const_string "0"))) (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "direct") - (set_attr "bdver1_decode" "double")]) - -(define_insn "*cmpi_sse" - [(set (reg:FPCMP FLAGS_REG) - (compare:FPCMP - (match_operand:MODEF 0 "register_operand" "x") - (match_operand:MODEF 1 "nonimmediate_operand" "xm")))] - "TARGET_SSE_MATH - && SSE_FLOAT_MODE_P (mode)" - "* return output_fp_compare (insn, operands, true, - mode == CCFPUmode);" - [(set_attr "type" "ssecomi") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "") - (set_attr "prefix_rep" "0") - (set (attr "prefix_data16") - (if_then_else (eq_attr "mode" "DF") - (const_string "1") - (const_string "0"))) - (set_attr "athlon_decode" "vector") - (set_attr "amdfam10_decode" "direct") - (set_attr "bdver1_decode" "double")]) + (set_attr "bdver1_decode" "double") + (set (attr "enabled") + (cond [(eq_attr "alternative" "0") + (symbol_ref "TARGET_MIX_SSE_I387") + ] + (symbol_ref "true")))]) (define_insn "*cmpi_i387" [(set (reg:FPCMP FLAGS_REG) @@ -4051,7 +4031,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))] - "TARGET_SSE2 && TARGET_MIX_SSE_I387" + "TARGET_SSE2 && TARGET_SSE_MATH" { switch (which_alternative) { @@ -4068,16 +4048,12 @@ } [(set_attr "type" "fmov,fmov,ssecvt") (set_attr "prefix" "orig,orig,maybe_vex") - (set_attr "mode" "SF,XF,DF")]) - -(define_insn "*extendsfdf2_sse" - [(set (match_operand:DF 0 "nonimmediate_operand" "=x") - (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && TARGET_SSE_MATH" - "%vcvtss2sd\t{%1, %d0|%d0, %1}" - [(set_attr "type" "ssecvt") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "DF")]) + (set_attr "mode" "SF,XF,DF") + (set (attr "enabled") + (cond [(eq_attr "alternative" "0,1") + (symbol_ref "TARGET_MIX_SSE_I387") + ] + (symbol_ref "true")))]) (define_insn "*extendsfdf2_i387" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m") @@ -4205,11 +4181,13 @@ (float_truncate:SF (match_operand:DF 1))) (clobber (match_operand:SF 2))])]) +;; SSE alternative doesn't depend on flag_unsafe_math_optimizations, +;; because nothing we do there is unsafe. (define_insn "*truncdfsf_fast_mixed" [(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x") (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f ,xm")))] - "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations" + "TARGET_SSE2 && TARGET_SSE_MATH" { switch (which_alternative) { @@ -4223,19 +4201,13 @@ } [(set_attr "type" "fmov,ssecvt") (set_attr "prefix" "orig,maybe_vex") - (set_attr "mode" "SF")]) - -;; Yes, this one doesn't depend on flag_unsafe_math_optimizations, -;; because nothing we do here is unsafe. -(define_insn "*truncdfsf_fast_sse" - [(set (match_operand:SF 0 "nonimmediate_operand" "=x") - (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && TARGET_SSE_MATH" - "%vcvtsd2ss\t{%1, %d0|%d0, %1}" - [(set_attr "type" "ssecvt") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "SF")]) + (set_attr "mode" "SF") + (set (attr "enabled") + (cond [(eq_attr "alternative" "0") + (symbol_ref "TARGET_MIX_SSE_I387 + && flag_unsafe_math_optimizations") + ] + (symbol_ref "true")))]) (define_insn "*truncdfsf_fast_i387" [(set (match_operand:SF 0 "nonimmediate_operand" "=fm") @@ -4863,7 +4835,7 @@ } }) -(define_insn "*float2_sse" +(define_insn "*float2_mixed" [(set (match_operand:MODEF 0 "register_operand" "=f,x,x") (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))] @@ -8836,17 +8808,13 @@ [(match_operand:MODEF 1 "register_operand" "0,x,0,0")])) (use (match_operand: 2 "nonimmediate_operand" "xm,0,X,X")) (clobber (reg:CC FLAGS_REG))] - "TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode)" - "#") - -(define_insn "*absneg2_sse" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,!r") - (match_operator:MODEF 3 "absneg_operator" - [(match_operand:MODEF 1 "register_operand" "0 ,x,0")])) - (use (match_operand: 2 "register_operand" "xm,0,X")) - (clobber (reg:CC FLAGS_REG))] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "#") + "#" + [(set (attr "enabled") + (cond [(eq_attr "alternative" "2") + (symbol_ref "TARGET_MIX_SSE_I387") + ] + (symbol_ref "true")))]) (define_insn "*absneg2_i387" [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r") @@ -13594,11 +13562,11 @@ ;; so use special patterns for add and mull. (define_insn "*fop__comm_mixed" - [(set (match_operand:MODEF 0 "register_operand" "=f,x,x") + [(set (match_operand:MODEF 0 "register_operand" "=f,x,v") (match_operator:MODEF 3 "binary_fp_operator" - [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,x") - (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,xm")]))] - "SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 + [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,v") + (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,vm")]))] + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3]) && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" @@ -13612,24 +13580,12 @@ (const_string "fop")))) (set_attr "isa" "*,noavx,avx") (set_attr "prefix" "orig,orig,vex") - (set_attr "mode" "")]) - -(define_insn "*fop__comm_sse" - [(set (match_operand:MODEF 0 "register_operand" "=x,v") - (match_operator:MODEF 3 "binary_fp_operator" - [(match_operand:MODEF 1 "nonimmediate_operand" "%0,v") - (match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && COMMUTATIVE_ARITH_P (operands[3]) - && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "* return output_387_binary_op (insn, operands);" - [(set (attr "type") - (if_then_else (match_operand:MODEF 3 "mult_operator") - (const_string "ssemul") - (const_string "sseadd"))) - (set_attr "isa" "noavx,avx") - (set_attr "prefix" "orig,vex") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "enabled") + (cond [(eq_attr "alternative" "0") + (symbol_ref "TARGET_MIX_SSE_I387") + ] + (const_string "*")))]) (define_insn "*fop__comm_i387" [(set (match_operand:MODEF 0 "register_operand" "=f")