From: Kenneth Graunke Date: Wed, 16 Jul 2014 03:40:55 +0000 (-0700) Subject: i965/fs: Use WE_all for gl_SampleID header register munging. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf1b5eee7f36af29d1d5caba3538ad4985e51f81;p=mesa.git i965/fs: Use WE_all for gl_SampleID header register munging. This code should execute without regard to the currently executing channels. Asking for gl_SampleID inside control flow might break in strange ways. It appears to break even at the top of the program in SIMD16 mode occasionally as well. Signed-off-by: Kenneth Graunke Reviewed-by: Matt Turner Reviewed-by: Chris Forbes Cc: mesa-stable@lists.freedesktop.org --- diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 53bd91b3180..1a5d9870d3f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1305,12 +1305,16 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir) * and then reading from it using vstride=1, width=4, hstride=0. * These computations hold good for 4x multisampling as well. */ - emit(BRW_OPCODE_AND, t1, - fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)), - fs_reg(0xc0)); - emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5)); + fs_inst *inst; + inst = emit(BRW_OPCODE_AND, t1, + fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)), + fs_reg(0xc0)); + inst->force_writemask_all = true; + inst = emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5)); + inst->force_writemask_all = true; /* This works for both SIMD8 and SIMD16 */ - emit(MOV(t2, brw_imm_v(0x3210))); + inst = emit(MOV(t2, brw_imm_v(0x3210))); + inst->force_writemask_all = true; /* This special instruction takes care of setting vstride=1, * width=4, hstride=0 of t2 during an ADD instruction. */