From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 07:03:11 +0000 (+0200)
Subject: Re-added clean after techmap in synth_xilinx
X-Git-Tag: yosys-0.9~182
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf1ba46fa029468869fb3af468d18ad72c8a9c4a;p=yosys.git

Re-added clean after techmap in synth_xilinx

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index da6c0a4b2..d66722195 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -124,6 +124,7 @@ struct SynthXilinxPass : public Pass
 		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
+		log("        clean\n");
 		log("\n");
 		log("    check:\n");
 		log("        hierarchy -check\n");
@@ -280,6 +281,7 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			Pass::call(design, "clean");
 		}
 
 		if (check_label(active, run_from, run_to, "check"))