From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 16 Jun 2021 12:07:34 +0000 (+0100)
Subject: ad fnmadd and fnmsubs to ISA pseudocode
X-Git-Tag: xlen-bcd~447
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf3a9ff250d9673853ba95bb58876c14f023b42c;p=openpower-isa.git

ad fnmadd and fnmsubs to ISA pseudocode
---

diff --git a/openpower/isa/fparith.mdwn b/openpower/isa/fparith.mdwn
index 1c80d0e1..a6a5e91a 100644
--- a/openpower/isa/fparith.mdwn
+++ b/openpower/isa/fparith.mdwn
@@ -155,7 +155,7 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1)
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 
 Special Registers Altered:
 
@@ -173,7 +173,43 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1)
+    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Negative Multiply-Add [Single]
+
+A-Form
+
+* fnmadds FRT,FRA,FRC,FRB (Rc=0)
+* fnmadds. FRT,FRA,FRC,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# Floating Negative Multiply-Sub [Single]
+
+A-Form
+
+* fnmsubs FRT,FRA,FRC,FRB (Rc=0)
+* fnmsubs. FRT,FRA,FRC,FRB (Rc=0)
+
+Pseudo-code:
+
+    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 
 Special Registers Altered:
 
diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index faef2d9a..7188f6cc 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -289,17 +289,21 @@ def FPMUL32(FRA, FRB):
     return cvt
 
 
-def FPMULADD32(FRA, FRB, FRC, sign):
+def FPMULADD32(FRA, FRB, FRC, addsign, mulsign):
     from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
     #return FPMUL64(FRA, FRB)
     #FRA = DOUBLE(SINGLE(FRA))
     #FRB = DOUBLE(SINGLE(FRB))
-    if sign == 1:
-        result = float(FRA) * float(FRB) + float(FRC)
-    elif sign == -1:
-        result = float(FRA) * float(FRB) - float(FRC)
-    elif sign == 0:
-        result = float(FRA) * float(FRB)
+    if addsign == 1:
+        result = float(FRC)
+    elif addsign == -1:
+        result = -float(FRC)
+    elif addsign == 0:
+        result = 0.0
+    if mulsign == 1:
+        result += float(FRA) * float(FRB)
+    elif mulsign == -1:
+        result -= float(FRA) * float(FRB)
     log ("FPMULADD32", FRA, FRB, FRC,
                        float(FRA), float(FRB), float(FRC),
                        result)