From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 16 Jul 2020 09:26:46 +0000 (+0100)
Subject: add mfmsr trap tests
X-Git-Tag: div_pipeline~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf433c5a8ae3478f8c31f50206cda6f95794d0af;p=soc.git

add mfmsr trap tests
---

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 146708ed..ed1f7089 100644
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -153,6 +153,20 @@ class TrapTestCase(FHDLTestCase):
                              initial_regs, initial_sprs,
                              initial_msr=msr)
 
+    def test_8_mfmsr(self):
+        lst = ["mfmsr 1"]
+        initial_regs = [0] * 32
+        msr = (~(1 << MSR.PR)) & 0xffffffffffffffff
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                                                      initial_msr=msr)
+
+    def test_9_mfmsr_priv(self):
+        lst = ["mfmsr 1"]
+        initial_regs = [0] * 32
+        msr = 1 << MSR.PR # set in "problem state"
+        self.run_tst_program(Program(lst, bigendian), initial_regs,
+                                                      initial_msr=msr)
+
     def test_999_illegal(self):
         # ok, um this is a bit of a cheat: use an instruction we know
         # is not implemented by either ISACaller or the core