From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 01:01:19 +0000 (+0100)
Subject: whoops changed name of ALUInputData to LogicalInputData
X-Git-Tag: div_pipeline~1053
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf43c0a63a6d7bd03eb3448f45c00b5fdc5ebebe;p=soc.git

whoops changed name of ALUInputData to LogicalInputData
---

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index 17a57335..f4fb3641 100644
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -31,7 +31,7 @@ class LogicalMainStage(PipeModBase):
         self.fields.create_specs()
 
     def ispec(self):
-        return ALUInputData(self.pspec)
+        return LogicalInputData(self.pspec)
 
     def ospec(self):
         return ALUOutputData(self.pspec) # TODO: ALUIntermediateData