From: lkcl Date: Fri, 11 Dec 2020 02:31:46 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1408 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf631472487c6c1b67484607a171b049933caea9;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index 7a925e015..7d318c6f0 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -24,7 +24,7 @@ twin predication and twin elwidth overrides is extremely important to have to be something like: -| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 21 | +| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 12 | 13 18 | 19 20 | | ----- | --- | --- | ---- | ---- | ----- | ----- | ----- | | subvl | sew | dew | ptyp | psrc | pdst | vspec | sat | @@ -51,7 +51,7 @@ With different bits being selectable (CR[0..3]) starting from the same CR makes these are of the form res = op(src1, src2, ...) -| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 21 | +| 0 1 | 2 3 | 4 5 | 6 | 7 9 | 10 18 | 19 20 | | ----- | --- | --- | ---- | ---- | ----- | ----- | | subvl | sew | dew | ptyp | pred | vspec | sat |