From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 00:46:53 +0000 (-0700)
Subject: Annotate SB_DFF* with abc_flop and abc_box_id
X-Git-Tag: working-ls180~1237^2~182
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf66416110f60b7dce10a78960898ceb52f51626;p=yosys.git

Annotate SB_DFF* with abc_flop and abc_box_id
---

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index dba563e37..a6f1fc9de 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2 *)
+(* abc_box_id = 22 *
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -127,25 +127,35 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, whitebox *)
+(* abc_box_id = 21, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+(* abc_box_id = 1, abc_flop *)
+`ifdef ABC_FLOPS
+    (* whitebox *)
+`endif
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+`ifndef ABC_FLOPS
 	always @(posedge C)
 		Q <= D;
+`else
+    assign Q = D;
+`endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 2, abc_flop *)
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 3, abc_flop *)
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -153,7 +163,8 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 4, abc_flop *)
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -161,7 +172,8 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 5, abc_flop *)
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -169,7 +181,8 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 6, abc_flop *)
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -177,7 +190,8 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 7, abc_flop *)
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -187,7 +201,8 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 8, abc_flop *)
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -195,7 +210,8 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 9, abc_flop *)
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -205,7 +221,8 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 10, abc_flop *)
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -215,18 +232,21 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+//(* abc_box_id = 11, abc_flop *)
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 12, abc_flop *)
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 13, abc_flop *)
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -234,7 +254,8 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 14, abc_flop *)
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -242,7 +263,8 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 15, abc_flop *)
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -250,7 +272,8 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 16, abc_flop *)
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -258,7 +281,8 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 17, abc_flop *)
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -268,7 +292,8 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 18, abc_flop *)
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -276,7 +301,8 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 19, abc_flop *)
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -286,7 +312,8 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 20, abc_flop *)
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;