From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 May 2020 03:56:54 +0000 (+0100)
Subject: dumb syntax error
X-Git-Tag: div_pipeline~1091
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf6eab17efcae7fa51238b8912ec7ff15e75b632;p=soc.git

dumb syntax error
---

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 76b00ea0..6efc5745 100644
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -89,7 +89,7 @@ class BranchMainStage(PipeModBase):
             comb += self.o.ctr.ok.eq(1)
             # take either all 64 bits or only 32 of post-incremented counter
             ctr_m = Signal(64, reset_less=True)
-            with m.If((op.is_32bit):
+            with m.If(op.is_32bit):
                 comb += ctr_m.eq(ctr[:32])
             with m.Else():
                 comb += ctr_m.eq(ctr)