From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 May 2023 12:44:09 +0000 (+0100)
Subject: move RG bit in CRops to Mode[2] from Mode[3] MSB0-numbering
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf79307700c7c83e78e861ccea01ba6b56ad1d8d;p=openpower-isa.git

move RG bit in CRops to Mode[2] from Mode[3] MSB0-numbering
---

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index f31ab561..7dc9e4b2 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -256,6 +256,7 @@ class SVP64MODEb(_Const):
     REDUCE = 2  # 0=normal predication 1=reduce mode
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
     RG = 4   # Reverse-gear on reduce
+    CROP_RG = 3   # Reverse-gear on reduce CR-ops
     # saturation mode
     N = 2  # saturation signed mode 0=signed 1=unsigned
     # ffirst and predicate result modes
diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 8cb54c4d..c1b66de3 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2311,7 +2311,7 @@ class CROpBaseRM(BaseRM):
 
 class CROpSimpleRM(PredicateBaseRM, ZZCombinedBaseRM, CROpBaseRM):
     """crop: simple mode"""
-    RG: BaseRM[20]
+    RG: BaseRM[21]
     dz: BaseRM[22]
     sz: BaseRM[23]
 
@@ -2323,8 +2323,8 @@ class CROpSimpleRM(PredicateBaseRM, ZZCombinedBaseRM, CROpBaseRM):
 
 
 class CROpMRRM(MRBaseRM, ZZCombinedBaseRM, CROpBaseRM):
-    """crop: scalar reduce mode (mapreduce), SUBVL=1"""
-    RG: BaseRM[20]
+    """crop: scalar reduce mode (mapreduce)"""
+    RG: BaseRM[21]
     dz: BaseRM[22]
     sz: BaseRM[23]