From: Kevin Lim <ktlim@umich.edu>
Date: Thu, 8 Jun 2006 20:58:50 +0000 (-0400)
Subject: Get O3 CPU mostly working in full system, and fix an FP bug that showed up.
X-Git-Tag: m5_2.0_beta1~36^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf79dba504e2ed47ea82dae6cfc71662d1bc25a0;p=gem5.git

Get O3 CPU mostly working in full system, and fix an FP bug that showed up.

It still does not yet handle retries.

src/cpu/base_dyn_inst.hh:
    Get working in full-system mode and fix some FP bugs.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/thread_state.hh:
    Get working in full system.
src/cpu/checker/o3_cpu_builder.cc:
    Checker does not take a MemObject as a simobj parameter.
src/cpu/o3/alpha_dyn_inst.hh:
    Fix up float regs.
src/cpu/o3/regfile.hh:
    Fix up an fp error, print out more useful output messages.

--HG--
extra : convert_revision : d7cc152a051c697f18b7ee9e14050fbf3ffa5966
---

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index e69e00d6c..263a24521 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -73,8 +73,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
     typedef TheISA::ExtMachInst ExtMachInst;
     // Logical register index type.
     typedef TheISA::RegIndex RegIndex;
-    // Integer register index type.
+    // Integer register type.
     typedef TheISA::IntReg IntReg;
+    // Floating point register type.
+    typedef TheISA::FloatReg FloatReg;
 
     // The DynInstPtr type.
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -442,17 +444,27 @@ class BaseDynInst : public FastAlloc, public RefCounted
         instResult.integer = val;
     }
 
-    void setFloatRegSingle(const StaticInst *si, int idx, float val)
+    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+    {
+        if (width == 32)
+            instResult.fp = val;
+        else if (width == 64)
+            instResult.dbl = val;
+        else
+            panic("Unsupported width!");
+    }
+
+    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
     {
         instResult.fp = val;
     }
 
-    void setFloatRegDouble(const StaticInst *si, int idx, double val)
+    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
     {
-        instResult.dbl = val;
+        instResult.integer = val;
     }
 
-    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+    void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
     {
         instResult.integer = val;
     }
@@ -657,14 +669,14 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
         return TheISA::genAlignmentFault();
     }
 
-    fault = cpu->translateDataReadReq(req);
+    fault = cpu->translateDataReadReq(req, thread);
 
     if (fault == NoFault) {
         effAddr = req->getVaddr();
         physEffAddr = req->getPaddr();
         memReqFlags = req->getFlags();
 
-#if FULL_SYSTEM
+#if 0
         if (cpu->system->memctrl->badaddr(physEffAddr)) {
             fault = TheISA::genMachineCheckFault();
             data = (T)-1;
@@ -712,13 +724,13 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
         return TheISA::genAlignmentFault();
     }
 
-    fault = cpu->translateDataWriteReq(req);
+    fault = cpu->translateDataWriteReq(req, thread);
 
     if (fault == NoFault) {
         effAddr = req->getVaddr();
         physEffAddr = req->getPaddr();
         memReqFlags = req->getFlags();
-#if FULL_SYSTEM
+#if 0
         if (cpu->system->memctrl->badaddr(physEffAddr)) {
             fault = TheISA::genMachineCheckFault();
         } else {
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b328a66c4..ebc02f7be 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -81,7 +81,6 @@ CheckerCPU::CheckerCPU(Params *p)
     itb = p->itb;
     dtb = p->dtb;
     systemPtr = NULL;
-    memPtr = NULL;
 #else
     process = p->process;
 #endif
@@ -94,44 +93,32 @@ CheckerCPU::~CheckerCPU()
 void
 CheckerCPU::setMemory(MemObject *mem)
 {
-    memPtr = mem;
 #if !FULL_SYSTEM
+    memPtr = mem;
     thread = new SimpleThread(this, /* thread_num */ 0, process,
                               /* asid */ 0, mem);
 
     thread->setStatus(ThreadContext::Suspended);
     tc = thread->getTC();
     threadContexts.push_back(tc);
-#else
-    if (systemPtr) {
-        thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
-
-        thread->setStatus(ThreadContext::Suspended);
-        tc = thread->getTC();
-        threadContexts.push_back(tc);
-        delete thread->kernelStats;
-        thread->kernelStats = NULL;
-    }
 #endif
 }
 
-#if FULL_SYSTEM
 void
 CheckerCPU::setSystem(System *system)
 {
+#if FULL_SYSTEM
     systemPtr = system;
 
-    if (memPtr) {
-        thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
+    thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
 
-        thread->setStatus(ThreadContext::Suspended);
-        tc = thread->getTC();
-        threadContexts.push_back(tc);
-        delete thread->kernelStats;
-        thread->kernelStats = NULL;
-    }
-}
+    thread->setStatus(ThreadContext::Suspended);
+    tc = thread->getTC();
+    threadContexts.push_back(tc);
+    delete thread->kernelStats;
+    thread->kernelStats = NULL;
 #endif
+}
 
 void
 CheckerCPU::setIcachePort(Port *icache_port)
@@ -350,7 +337,7 @@ CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 Addr
 CheckerCPU::dbg_vtophys(Addr addr)
 {
-    return vtophys(xcProxy, addr);
+    return vtophys(tc, addr);
 }
 #endif // FULL_SYSTEM
 
@@ -601,7 +588,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
 
         if (fault != NoFault) {
 #if FULL_SYSTEM
-            fault->invoke(xcProxy);
+            fault->invoke(tc);
             willChangePC = true;
             newPC = thread->readPC();
             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
@@ -630,7 +617,7 @@ Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
         int count = 0;
         do {
             oldpc = thread->readPC();
-            system->pcEventQueue.service(xcProxy);
+            system->pcEventQueue.service(tc);
             count++;
         } while (oldpc != thread->readPC());
         if (count > 1) {
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index d1a0ba684..c9986d228 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -99,7 +99,6 @@ class CheckerCPU : public BaseCPU
 #if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
-        FunctionalMemory *mem;
 #else
         Process *process;
 #endif
@@ -116,11 +115,9 @@ class CheckerCPU : public BaseCPU
 
     MemObject *memPtr;
 
-#if FULL_SYSTEM
     void setSystem(System *system);
 
     System *systemPtr;
-#endif
 
     void setIcachePort(Port *icache_port);
 
@@ -327,7 +324,7 @@ class CheckerCPU : public BaseCPU
     int readIntrFlag() { return thread->readIntrFlag(); }
     void setIntrFlag(int val) { thread->setIntrFlag(val); }
     bool inPalMode() { return thread->inPalMode(); }
-    void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+    void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
     // Assume that the normal CPU's call to syscall was successful.
diff --git a/src/cpu/checker/o3_cpu_builder.cc b/src/cpu/checker/o3_cpu_builder.cc
index 5973ac58e..59a6c7158 100644
--- a/src/cpu/checker/o3_cpu_builder.cc
+++ b/src/cpu/checker/o3_cpu_builder.cc
@@ -65,7 +65,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
 #if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;
@@ -95,7 +94,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
 #if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(profile, ""),
@@ -138,7 +136,6 @@ CREATE_SIM_OBJECT(O3Checker)
 #if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
-    params->mem = mem;
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 4340bd516..c0ac8f01d 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -81,8 +81,6 @@ class CheckerThreadContext : public ThreadContext
 
     int readCpuId() { return actualTC->readCpuId(); }
 
-    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
-
 #if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
@@ -93,7 +91,16 @@ class CheckerThreadContext : public ThreadContext
     AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
     Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+
+    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+
+    VirtualPort *getVirtPort(ThreadContext *tc = NULL)
+    { return actualTC->getVirtPort(); }
+
+    void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
 #else
+    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 #endif
 
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 3449454bd..974b230f3 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -77,6 +77,11 @@ class AlphaFullCPU : public FullO3CPU<Impl>
      * external objects try to update state through this interface,
      * the CPU will create an event to squash all in-flight
      * instructions in order to ensure state is maintained correctly.
+     * It must be defined specifically for the AlphaFullCPU because
+     * not all architectural state is located within the O3ThreadState
+     * (such as the commit PC, and registers), and specific actions
+     * must be taken when using this interface (such as squashing all
+     * in-flight instructions when doing a write to this interface).
      */
     class AlphaTC : public ThreadContext
     {
@@ -96,8 +101,6 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         /** Reads this CPU's ID. */
         virtual int readCpuId() { return cpu->cpu_id; }
 
-        virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
-
 #if FULL_SYSTEM
         /** Returns a pointer to the system. */
         virtual System *getSystemPtr() { return cpu->system; }
@@ -114,7 +117,15 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         /** Returns a pointer to this thread's kernel statistics. */
         virtual Kernel::Statistics *getKernelStats()
         { return thread->kernelStats; }
+
+        virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+        virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
+
+        void delVirtPort(VirtualPort *vp);
 #else
+        virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+
         /** Returns a pointer to this thread's process. */
         virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 #endif
@@ -301,43 +312,40 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 #if FULL_SYSTEM
     /** Translates instruction requestion. */
-    Fault translateInstReq(RequestPtr &req)
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
     {
-        return itb->translate(req);
+        return itb->translate(req, thread->getTC());
     }
 
     /** Translates data read request. */
-    Fault translateDataReadReq(RequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
     {
-        return dtb->translate(req, false);
+        return dtb->translate(req, thread->getTC(), false);
     }
 
     /** Translates data write request. */
-    Fault translateDataWriteReq(RequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
     {
-        return dtb->translate(req, true);
+        return dtb->translate(req, thread->getTC(), true);
     }
 
 #else
     /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req)
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
     {
-        int tid = req->getThreadNum();
-        return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+        return thread->getProcessPtr()->pTable->translate(req);
     }
 
     /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
     {
-        int tid = req->getThreadNum();
-        return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+        return thread->getProcessPtr()->pTable->translate(req);
     }
 
     /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
     {
-        int tid = req->getThreadNum();
-        return this->thread[tid]->getProcessPtr()->pTable->translate(req);
+        return thread->getProcessPtr()->pTable->translate(req);
     }
 
 #endif
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 2debe074b..fb2fea8e6 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -46,6 +46,7 @@
 #include "arch/isa_traits.hh"
 #include "cpu/quiesce_event.hh"
 #include "kern/kernel_stats.hh"
+#include "sim/system.hh"
 #endif
 
 using namespace TheISA;
@@ -67,7 +68,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
 #if FULL_SYSTEM
         // SMT is not supported in FS mode yet.
         assert(this->numThreads == 1);
-        this->thread[i] = new Thread(this, 0, params->mem);
+        this->thread[i] = new Thread(this, 0);
         this->thread[i]->setStatus(ThreadContext::Suspended);
 #else
         if (i < params->workload.size()) {
@@ -128,14 +129,14 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
         FunctionalPort *phys_port;
         VirtualPort *virt_port;
         phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
-                                               cpu->name(), tid));
-        mem_port = system->physmem->getPort("functional");
+                                                name(), i));
+        mem_port = this->system->physmem->getPort("functional");
         mem_port->setPeer(phys_port);
         phys_port->setPeer(mem_port);
 
         virt_port = new VirtualPort(csprintf("%s-%d-vport",
-                                            cpu->name(), tid));
-        mem_port = system->physmem->getPort("functional");
+                                             name(), i));
+        mem_port = this->system->physmem->getPort("functional");
         mem_port->setPeer(virt_port);
         virt_port->setPeer(mem_port);
 
@@ -182,6 +183,23 @@ AlphaFullCPU<Impl>::regStats()
 }
 
 #if FULL_SYSTEM
+template <class Impl>
+VirtualPort *
+AlphaFullCPU<Impl>::AlphaTC::getVirtPort(ThreadContext *src_tc)
+{
+    if (!src_tc)
+        return thread->getVirtPort();
+
+    VirtualPort *vp;
+    Port *mem_port;
+
+    vp = new VirtualPort("tc-vport", src_tc);
+    mem_port = cpu->system->physmem->getPort("functional");
+    mem_port->setPeer(vp);
+    vp->setPeer(mem_port);
+    return vp;
+}
+
 template <class Impl>
 void
 AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
@@ -195,7 +213,6 @@ void
 AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-    assert(getMemPort() == old_context->getMemPort());
 #if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
 #else
@@ -232,6 +249,16 @@ AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
     thread->trapPending = false;
 }
 
+#if FULL_SYSTEM
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaTC::delVirtPort(VirtualPort *vp)
+{
+    delete vp->getPeer();
+    delete vp;
+}
+#endif
+
 template <class Impl>
 void
 AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha_dyn_inst.hh
index 143ffe7e4..36a08c4a7 100644
--- a/src/cpu/o3/alpha_dyn_inst.hh
+++ b/src/cpu/o3/alpha_dyn_inst.hh
@@ -207,26 +207,26 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val, width);
-        BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
+        BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
     }
 
     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
     {
         this->cpu->setFloatReg(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
+        BaseDynInst<Impl>::setFloatReg(si, idx, val);
     }
 
     void setFloatRegBits(const StaticInst *si, int idx,
             FloatRegBits val, int width)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
-        this->instResult.integer = val;
+        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
     }
 
     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
     {
         this->cpu->setFloatRegBits(_destRegIdx[idx], val);
-        BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
+        BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
     }
 
     /** Returns the physical register index of the i'th destination
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 8ee47e907..ceb2918e0 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -907,7 +907,7 @@ DefaultCommit<Impl>::commitInsts()
                                !thread[tid]->trapPending);
                     oldpc = PC[tid];
                     cpu->system->pcEventQueue.service(
-                        thread[tid]->getXCProxy());
+                        thread[tid]->getTC());
                     count++;
                 } while (oldpc != PC[tid]);
                 if (count > 1) {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c5f78d63d..788c6b164 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -122,7 +122,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
 
 #if FULL_SYSTEM
       system(params->system),
-      memCtrl(system->memctrl),
       physmem(system->physmem),
 #endif // FULL_SYSTEM
       mem(params->mem),
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 8e482f1e5..7c8729749 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -474,8 +474,6 @@ class FullO3CPU : public BaseFullCPU
     /** Pointer to the system. */
     System *system;
 
-    /** Pointer to the memory controller. */
-    MemoryController *memCtrl;
     /** Pointer to physical memory. */
     PhysicalMemory *physmem;
 #endif
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f3793db6d..152b69788 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -43,8 +43,6 @@
 #include "arch/tlb.hh"
 #include "arch/vtophys.hh"
 #include "base/remote_gdb.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
 #include "sim/system.hh"
 #endif // FULL_SYSTEM
 
@@ -531,7 +529,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
 
     // Translate the instruction request.
 //#if FULL_SYSTEM
-    fault = cpu->translateInstReq(mem_req);
+    fault = cpu->translateInstReq(mem_req, cpu->thread[tid]);
 //#else
 //    fault = pTable->translate(memReq[tid]);
 //#endif
@@ -542,7 +540,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     // If translation was successful, attempt to read the first
     // instruction.
     if (fault == NoFault) {
-#if FULL_SYSTEM
+#if 0
         if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
             memReq[tid]->flags & UNCACHEABLE) {
             DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index a142b7102..ade5e4e56 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -96,7 +96,7 @@ class PhysRegFile
         assert(reg_idx < numPhysicalIntRegs);
 
         DPRINTF(IEW, "RegFile: Access to int register %i, has data "
-                "%i\n", int(reg_idx), intRegFile[reg_idx]);
+                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
         return intRegFile[reg_idx];
     }
 
@@ -110,7 +110,7 @@ class PhysRegFile
         FloatReg floatReg = floatRegFile[reg_idx].d;
 
         DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
-                "data %8.8d\n", int(reg_idx), (double)floatReg);
+                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
 
         return floatReg;
     }
@@ -126,7 +126,7 @@ class PhysRegFile
         FloatReg floatReg = floatRegFile[reg_idx].d;
 
         DPRINTF(IEW, "RegFile: Access to float register %i, has "
-                "data %8.8d\n", int(reg_idx), (double)floatReg);
+                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
 
         return floatReg;
     }
@@ -141,8 +141,8 @@ class PhysRegFile
 
         FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
 
-        DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
-                "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
+                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
 
         return floatRegBits;
     }
@@ -157,7 +157,7 @@ class PhysRegFile
         FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
 
         DPRINTF(IEW, "RegFile: Access to float register %i as int, "
-                "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
 
         return floatRegBits;
     }
@@ -167,7 +167,7 @@ class PhysRegFile
     {
         assert(reg_idx < numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
+        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
                 int(reg_idx), val);
 
         if (reg_idx != TheISA::ZeroReg)
@@ -182,11 +182,11 @@ class PhysRegFile
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
-                int(reg_idx), (double)val);
+        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
+                int(reg_idx), (uint64_t)val);
 
         if (reg_idx != TheISA::ZeroReg)
-            floatRegFile[reg_idx].d = width;
+            floatRegFile[reg_idx].d = val;
     }
 
     /** Sets a double precision floating point register to the given value. */
@@ -197,8 +197,8 @@ class PhysRegFile
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
-                int(reg_idx), (double)val);
+        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
+                int(reg_idx), (uint64_t)val);
 
         if (reg_idx != TheISA::ZeroReg)
             floatRegFile[reg_idx].d = val;
@@ -212,7 +212,7 @@ class PhysRegFile
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                 int(reg_idx), (uint64_t)val);
 
         floatRegFile[reg_idx].q = val;
@@ -225,7 +225,7 @@ class PhysRegFile
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                 int(reg_idx), (uint64_t)val);
 
         floatRegFile[reg_idx].q = val;
@@ -263,10 +263,10 @@ class PhysRegFile
 
   public:
     /** (signed) integer register file. */
-    std::vector<IntReg> intRegFile;
+    IntReg *intRegFile;
 
     /** Floating point register file. */
-    std::vector<PhysFloatReg> floatRegFile;
+    PhysFloatReg *floatRegFile;
 
     /** Miscellaneous register file. */
     MiscRegFile miscRegs[Impl::MaxThreads];
@@ -296,15 +296,15 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
     : numPhysicalIntRegs(_numPhysicalIntRegs),
       numPhysicalFloatRegs(_numPhysicalFloatRegs)
 {
-    intRegFile.resize(numPhysicalIntRegs);
-    floatRegFile.resize(numPhysicalFloatRegs);
+    intRegFile = new IntReg[numPhysicalIntRegs];
+    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
 
     for (int i = 0; i < Impl::MaxThreads; ++i) {
         miscRegs[i].clear();
     }
 
-    //memset(intRegFile, 0, sizeof(*intRegFile));
-    //memset(floatRegFile, 0, sizeof(*floatRegFile));
+    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
+    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
 }
 
 #endif
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1fbf24931..b6535baa1 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -75,7 +75,7 @@ struct O3ThreadState : public ThreadState {
     bool trapPending;
 
 #if FULL_SYSTEM
-    O3ThreadState(FullCPU *_cpu, int _thread_num, )
+    O3ThreadState(FullCPU *_cpu, int _thread_num)
         : ThreadState(-1, _thread_num),
           inSyscall(0), trapPending(0)
     { }
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 55e3813ae..e9550c39b 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -113,8 +113,6 @@ class OzoneCPU : public BaseCPU
 
         int readCpuId() { return thread->cpuId; }
 
-        TranslatingPort *getMemPort() { return /*thread->port*/NULL; }
-
 #if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
 
@@ -125,7 +123,17 @@ class OzoneCPU : public BaseCPU
         AlphaDTB * getDTBPtr() { return cpu->dtb; }
 
         Kernel::Statistics *getKernelStats() { return thread->kernelStats; }
+
+        FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+
+        VirtualPort *getVirtPort(ThreadContext *tc = NULL)
+        { return thread->getVirtPort(tc); }
+
+        void delVirtPort(VirtualPort *vp)
+        { thread->delVirtPort(vp); }
 #else
+        TranslatingPort *getMemPort() { return thread->port; }
+
         Process *getProcessPtr() { return thread->process; }
 #endif
 
@@ -363,23 +371,9 @@ class OzoneCPU : public BaseCPU
     AlphaITB *itb;
     AlphaDTB *dtb;
     System *system;
-
-    // the following two fields are redundant, since we can always
-    // look them up through the system pointer, but we'll leave them
-    // here for now for convenience
-    MemoryController *memctrl;
     PhysicalMemory *physmem;
 #endif
 
-    // L1 instruction cache
-//    MemInterface *icacheInterface;
-
-    // L1 data cache
-//    MemInterface *dcacheInterface;
-
-    /** Pointer to memory. */
-    FunctionalMemory *mem;
-
     FrontEnd *frontEnd;
 
     BackEnd *backEnd;
@@ -424,19 +418,19 @@ class OzoneCPU : public BaseCPU
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault translateInstReq(Request *req)
     {
-        return itb->translate(req);
+        return itb->translate(req, tc);
     }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault translateDataReadReq(Request *req)
     {
-        return dtb->translate(req, false);
+        return dtb->translate(req, tc, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault translateDataWriteReq(Request *req)
     {
-        return dtb->translate(req, true);
+        return dtb->translate(req, tc, true);
     }
 
 #else
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index d5fe7ef48..299878c29 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -62,8 +62,8 @@ struct OzoneThreadState : public ThreadState {
     typedef TheISA::MiscReg MiscReg;
 
 #if FULL_SYSTEM
-    OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
-        : ThreadState(-1, _thread_num, _mem),
+    OzoneThreadState(FullCPU *_cpu, int _thread_num)
+        : ThreadState(-1, _thread_num),
           inSyscall(0), trapPending(0)
     {
         memset(&regs, 0, sizeof(TheISA::RegFile));
@@ -76,9 +76,9 @@ struct OzoneThreadState : public ThreadState {
         memset(&regs, 0, sizeof(TheISA::RegFile));
     }
 
-    OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
+    OzoneThreadState(FullCPU *_cpu, int _thread_num,
                      int _asid)
-        : ThreadState(-1, _thread_num, _mem, NULL, _asid),
+        : ThreadState(-1, _thread_num, NULL, NULL, _asid),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         memset(&regs, 0, sizeof(TheISA::RegFile));
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 01ad4625c..de9b2f14e 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -88,8 +88,12 @@ struct ThreadState {
 
     Kernel::Statistics *getKernelStats() { return kernelStats; }
 
+    FunctionalPort *getPhysPort() { return physPort; }
+
     void setPhysPort(FunctionalPort *port) { physPort = port; }
 
+    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
+
     void setVirtPort(VirtualPort *port) { virtPort = port; }
 #else
     Process *getProcessPtr() { return process; }
@@ -149,6 +153,7 @@ struct ThreadState {
     // Index of hardware thread context on the CPU that this represents.
     int tid;
 
+  public:
     /** Last time activate was called on this thread. */
     Tick lastActivate;
 
@@ -187,6 +192,7 @@ struct ThreadState {
      */
     TheISA::MachInst inst;
 
+  public:
     /**
      * Temporary storage to pass the source address from copy_load to
      * copy_store.
@@ -199,7 +205,6 @@ struct ThreadState {
      */
     Addr copySrcPhysAddr;
 
-  public:
     /*
      * number of executed instructions, for matching with syscall trace
      * points in EIO files.