From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 17 Jul 2007 22:28:48 +0000 (-0700)
Subject: Add in operand which holds the condition code bits of the flag register.
X-Git-Tag: m5_2.0_beta4~297^2~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf846d5205c021a04ab1a8e830d9cb86be0bda6e;p=gem5.git

Add in operand which holds the condition code bits of the flag register.

--HG--
extra : convert_revision : 416052f41fccc8286b3bdbe8d559512a761224f2
---

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index b2ac17d66..83df583ea 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -103,5 +103,6 @@ def operands {{
         'Index':         ('IntReg', 'uqw', 'index', 'IsInteger', 5),
         'Data':          ('IntReg', 'uqw', 'data', 'IsInteger', 6),
         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
+        'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};