From: whitequark Date: Sat, 22 Dec 2018 05:27:42 +0000 (+0000) Subject: back.rtlil: always initialize the entire memory. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf8b9de08ea40e42f23374807690775cd2aa776d;p=nmigen.git back.rtlil: always initialize the entire memory. This avoids reading 'x from the memory in simulation. In general, FPGA memories can only be initialized in block granularity, and zero-initializing is cheap, so this is not a significant issue with resource consumption. --- diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index c2b8809..6fff6d2 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -624,7 +624,11 @@ def convert_fragment(builder, fragment, name, top): memories[memory] = module.memory(width=memory.width, size=memory.depth, name=memory.name) addr_bits = bits_for(memory.depth) - for addr, data in enumerate(memory.init): + for addr in range(memory.depth): + if addr < len(memory.init): + data = memory.init[addr] + else: + data = 0 module.cell("$meminit", ports={ "\\ADDR": rhs_compiler(ast.Const(addr, addr_bits)), "\\DATA": rhs_compiler(ast.Const(data, memory.width)),