From: Bilyan Borisov <bilyan.borisov@arm.com>
Date: Tue, 24 Nov 2015 11:22:48 +0000 (+0000)
Subject: [AARCH64][PATCH 3/3] Adding tests to check proper error reporting of out of...
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfa55545f9aff809f267babb110b1037e164a1cd;p=gcc.git

[AARCH64][PATCH 3/3] Adding tests to check proper error reporting of out of...

[AARCH64][PATCH 3/3] Adding tests to check proper error reporting of out
of bounds accesses to vmulx_lane* NEON intrinsics

gcc/testsuite/

	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c:
	New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c:
	New.

From-SVN: r230800
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d5a1023b94d..2b31f8c71b2 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,30 @@
+2015-11-24  Bilyan Borisov  <bilyan.borisov@arm.com>
+
+	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c:
+	New.
+	* gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c:
+	New.
+
 2015-11-24  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR middle-end/68375
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c
new file mode 100644
index 00000000000..1494633e606
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32x2_t
+f_vmulx_lane_f32 (float32x2_t v1, float32x2_t v2)
+{
+  float32x2_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vmulx_lane_f32 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vmulx_lane_f32 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c
new file mode 100644
index 00000000000..3fdb557d1bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x1_t
+f_vmulx_lane_f64 (float64x1_t v1, float64x1_t v2)
+{
+  float64x1_t res;
+  /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vmulx_lane_f64 (v1, v2, -1);
+  /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
+  res = vmulx_lane_f64 (v1, v2, 1);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c
new file mode 100644
index 00000000000..1f8dfd0a097
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32x2_t
+f_vmulx_laneq_f32 (float32x2_t v1, float32x4_t v2)
+{
+  float32x2_t res;
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulx_laneq_f32 (v1, v2, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulx_laneq_f32 (v1, v2, 4);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c
new file mode 100644
index 00000000000..8d54ebe74a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_laneq_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x1_t
+f_vmulx_laneq_f64 (float64x1_t v1, float64x2_t v2)
+{
+  float64x1_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulx_laneq_f64 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulx_laneq_f64 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c
new file mode 100644
index 00000000000..0db5cd0f73e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64_t
+f_vmulxd_lane_f64 (float64_t v1, float64x1_t v2)
+{
+  float64_t res;
+  /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  res = vmulxd_lane_f64 (v1, v2, -1);
+  /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  res = vmulxd_lane_f64 (v1, v2, 1);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c
new file mode 100644
index 00000000000..6df1a0d55b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxd_laneq_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64_t
+f_vmulxd_laneq_f64 (float64_t v1, float64x2_t v2)
+{
+  float64_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxd_laneq_f64 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxd_laneq_f64 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c
new file mode 100644
index 00000000000..3fee966230d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32x4_t
+f_vmulxq_lane_f32 (float32x4_t v1, float32x2_t v2)
+{
+  float32x4_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vmulxq_lane_f32 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
+  res = vmulxq_lane_f32 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c
new file mode 100644
index 00000000000..2acddf2e886
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_lane_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x2_t
+f_vmulxq_lane_f64 (float64x2_t v1, float64x1_t v2)
+{
+  float64x2_t res;
+  /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  res = vmulxq_lane_f64 (v1, v2, -1);
+  /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  res = vmulxq_lane_f64 (v1, v2, 1);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c
new file mode 100644
index 00000000000..bbd3e00c844
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32x4_t
+f_vmulxq_laneq_f32 (float32x4_t v1, float32x4_t v2)
+{
+  float32x4_t res;
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulxq_laneq_f32 (v1, v2, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulxq_laneq_f32 (v1, v2, 4);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c
new file mode 100644
index 00000000000..0284193c42f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxq_laneq_f64_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float64x2_t
+f_vmulxq_laneq_f64 (float64x2_t v1, float64x2_t v2)
+{
+  float64x2_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxq_laneq_f64 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxq_laneq_f64 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c
new file mode 100644
index 00000000000..73a6e7110fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_lane_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32_t
+f_vmulxs_lane_f32 (float32_t v1, float32x2_t v2)
+{
+  float32_t res;
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxs_lane_f32 (v1, v2, -1);
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  res = vmulxs_lane_f32 (v1, v2, 2);
+  return res;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c
new file mode 100644
index 00000000000..132ffb1c096
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxs_laneq_f32_indices_1.c
@@ -0,0 +1,16 @@
+#include <arm_neon.h>
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
+/* { dg-skip-if "" { arm*-*-* } } */
+
+float32_t
+f_vmulxs_laneq_f32 (float32_t v1, float32x4_t v2)
+{
+  float32_t res;
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulxs_laneq_f32 (v1, v2, -1);
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  res = vmulxs_laneq_f32 (v1, v2, 4);
+  return res;
+}