From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 30 Nov 2013 22:06:51 +0000 (+0100)
Subject: norflash16: fix LSB
X-Git-Tag: 24jan2021_ls180~2761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfb90747559d9886a53220edc9f83f2c0ec440db;p=litex.git

norflash16: fix LSB
---

diff --git a/misoclib/norflash16/__init__.py b/misoclib/norflash16/__init__.py
index ba0f0090..12ae1e71 100644
--- a/misoclib/norflash16/__init__.py
+++ b/misoclib/norflash16/__init__.py
@@ -8,14 +8,11 @@ class NorFlash16(Module):
 
 		###
 
-		adr_width = flen(pads.adr) + 1
-		adr_r = Signal(adr_width) # in 16-bit memory words
 		data = TSTriple(16)
 		lsb = Signal()
 
 		self.specials += data.get_tristate(pads.d)
 		self.comb += [
-			pads.adr.eq(Cat(lsb, adr_r[1:])),
 			data.oe.eq(pads.oe_n),
 			pads.ce_n.eq(0)
 		]
@@ -31,7 +28,7 @@ class NorFlash16(Module):
 
 			# Register data/address to avoid off-chip glitches
 			If(self.bus.cyc & self.bus.stb,
-				adr_r.eq(Cat(0, self.bus.adr)),
+				pads.adr.eq(Cat(lsb, self.bus.adr)),
 				If(self.bus.we,
 					# Only 16-bit writes are supported. Assume sel=0011 or 1100.
 					If(self.bus.sel[0],