From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 12 Mar 2019 13:14:17 +0000 (+0000)
Subject: add example buffered pipe
X-Git-Tag: ls180-24jan2020~1688
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfc989aa8b0d4c19a15c6e0d7210dde46bb480e8;p=ieee754fpu.git

add example buffered pipe
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 20e91e4e..aedf8dce 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -1,3 +1,6 @@
+""" nmigen implementation of buffered pipeline stage, based on zipcpu:
+    https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
+"""
 from nmigen import Signal, Cat, Const, Mux, Module
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil