From: Patrick Urban <patrick.urban@web.de>
Date: Tue, 14 Sep 2021 13:10:32 +0000 (+0200)
Subject: synth_gatemate: Apply review remarks
X-Git-Tag: yosys-0.12~29
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfcc38582a4464b0a0551b842ea7a22c6f9a559d;p=yosys.git

synth_gatemate: Apply review remarks
---

diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v
index 3a1fcd550..f6fe6a3e1 100644
--- a/techlibs/gatemate/cells_bb.v
+++ b/techlibs/gatemate/cells_bb.v
@@ -45,7 +45,7 @@ module CC_PLL_ADV #(
 );
 endmodule
 
-(* blackbox *)
+(* blackbox *) (* keep *)
 module CC_SERDES #(
 	parameter SERDES_CFG = ""
 )(
@@ -122,3 +122,70 @@ module CC_CFG_CTRL(
 	input VALID
 );
 endmodule
+
+(* blackbox *)
+module CC_FIFO_40K (
+	output A_ECC_1B_ERR,
+	output B_ECC_1B_ERR,
+	output A_ECC_2B_ERR,
+	output B_ECC_2B_ERR,
+	// FIFO pop port
+	output [39:0] A_DO,
+	output [39:0] B_DO,
+	(* clkbuf_sink *)
+	input  A_CLK,
+	input  A_EN,
+	// FIFO push port
+	input  [39:0] A_DI,
+	input  [39:0] B_DI,
+	input  [39:0] A_BM,
+	input  [39:0] B_BM,
+	(* clkbuf_sink *)
+	input  B_CLK,
+	input  B_EN,
+	input  B_WE,
+	// FIFO control
+	input  F_RST_N,
+	input  [12:0] F_ALMOST_FULL_OFFSET,
+	input  [12:0] F_ALMOST_EMPTY_OFFSET,
+	// FIFO status signals
+	output F_FULL,
+	output F_EMPTY,
+	output F_ALMOST_FULL,
+	output F_ALMOST_EMPTY,
+	output F_RD_ERROR,
+	output F_WR_ERROR,
+	output [15:0] F_RD_PTR,
+	output [15:0] F_WR_PTR
+);
+	// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
+	parameter LOC = "UNPLACED";
+
+	// Offset configuration
+	parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
+	parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
+
+	// Port Widths
+	parameter A_WIDTH = 0;
+	parameter B_WIDTH = 0;
+
+	// RAM and Write Modes
+	parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
+	parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
+
+	// Inverting Control Pins
+	parameter A_CLK_INV = 1'b0;
+	parameter B_CLK_INV = 1'b0;
+	parameter A_EN_INV = 1'b0;
+	parameter B_EN_INV = 1'b0;
+	parameter A_WE_INV = 1'b0;
+	parameter B_WE_INV = 1'b0;
+
+	// Output Register
+	parameter A_DO_REG = 1'b0;
+	parameter B_DO_REG = 1'b0;
+
+	// Error Checking and Correction
+	parameter A_ECC_EN  = 1'b0;
+	parameter B_ECC_EN  = 1'b0;
+endmodule
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index 0d241012f..1f6d9d5ef 100644
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -294,7 +294,7 @@ module CC_DFF #(
 	assign en  = (EN_INV)  ?  ~EN :  EN;
 	assign sr  = (SR_INV)  ?  ~SR :  SR;
 
-	initial Q = 0;
+	initial Q = 1'bX;
 
 	always @(posedge clk or posedge sr)
 	begin
@@ -323,7 +323,7 @@ module CC_DLT #(
 	assign en  = (G_INV) ? ~G : G;
 	assign sr  = (SR_INV) ? ~SR : SR;
 
-	initial Q = 0;
+	initial Q = 1'bX;
 
 	always @(*)
 	begin
@@ -409,14 +409,9 @@ endmodule
 module CC_MX2 (
 	input  D0, D1,
 	input  S0,
-	output reg Y
+	output Y
 );
-	always @(*) begin
-		case (S0)
-			1'b0: Y <= D0;
-			1'b1: Y <= D1;
-		endcase
-	end
+	assign Y = S0 ? D1 : D0;
 
 	specify
 		(D0 => Y) = (0:0:0, 0:0:0);
@@ -429,16 +424,10 @@ endmodule
 module CC_MX4 (
 	input  D0, D1, D2, D3,
 	input  S0, S1,
-	output reg Y
+	output Y
 );
-	always @(*) begin
-		case ({S1, S0})
-			2'b00: Y <= D0;
-			2'b01: Y <= D1;
-			2'b10: Y <= D2;
-			2'b11: Y <= D3;
-		endcase
-	end
+	assign Y = S1 ? (S0 ? D3 : D2) :
+					(S0 ? D1 : D0);
 
 	specify
 		(D0 => Y) = (0:0:0, 0:0:0);
@@ -455,20 +444,12 @@ module CC_MX8 (
 	input  D0, D1, D2, D3,
 	input  D4, D5, D6, D7,
 	input  S0, S1, S2,
-	output reg Y
+	output Y
 );
-	always @(*) begin
-		case ({S2, S1, S0})
-			3'b000: Y <= D0;
-			3'b001: Y <= D1;
-			3'b010: Y <= D2;
-			3'b011: Y <= D3;
-			3'b100: Y <= D4;
-			3'b101: Y <= D5;
-			3'b110: Y <= D6;
-			3'b111: Y <= D7;
-		endcase
-	end
+	assign Y = S2 ? (S1 ? (S0 ? D7 : D6) :
+						  (S0 ? D5 : D4)) :
+					(S1 ? (S0 ? D3 : D2) :
+						  (S0 ? D1 : D0));
 
 	specify
 		(D0 => Y) = (0:0:0, 0:0:0);
@@ -531,7 +512,6 @@ module CC_BUFG (
 endmodule
 
 
-(* blackbox *)
 module CC_BRAM_20K (
 	output [19:0] A_DO,
 	output [19:0] B_DO,
@@ -941,7 +921,6 @@ module CC_BRAM_20K (
 endmodule
 
 
-(* blackbox *)
 module CC_BRAM_40K (
 	output [39:0] A_DO,
 	output [39:0] B_DO,
@@ -1504,71 +1483,3 @@ module CC_BRAM_40K (
 		end
    endgenerate
 endmodule
-
-
-(* blackbox *)
-module CC_FIFO_40K (
-	output A_ECC_1B_ERR,
-	output B_ECC_1B_ERR,
-	output A_ECC_2B_ERR,
-	output B_ECC_2B_ERR,
-	// FIFO pop port
-	output [39:0] A_DO,
-	output [39:0] B_DO,
-	(* clkbuf_sink *)
-	input  A_CLK,
-	input  A_EN,
-	// FIFO push port
-	input  [39:0] A_DI,
-	input  [39:0] B_DI,
-	input  [39:0] A_BM,
-	input  [39:0] B_BM,
-	(* clkbuf_sink *)
-	input  B_CLK,
-	input  B_EN,
-	input  B_WE,
-	// FIFO control
-	input  F_RST_N,
-	input  [12:0] F_ALMOST_FULL_OFFSET,
-	input  [12:0] F_ALMOST_EMPTY_OFFSET,
-	// FIFO status signals
-	output F_FULL,
-	output F_EMPTY,
-	output F_ALMOST_FULL,
-	output F_ALMOST_EMPTY,
-	output F_RD_ERROR,
-	output F_WR_ERROR,
-	output [15:0] F_RD_PTR,
-	output [15:0] F_WR_PTR
-);
-	// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
-	parameter LOC = "UNPLACED";
-
-	// Offset configuration
-	parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
-	parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
-
-	// Port Widths
-	parameter A_WIDTH = 0;
-	parameter B_WIDTH = 0;
-
-	// RAM and Write Modes
-	parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
-	parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
-
-	// Inverting Control Pins
-	parameter A_CLK_INV = 1'b0;
-	parameter B_CLK_INV = 1'b0;
-	parameter A_EN_INV = 1'b0;
-	parameter B_EN_INV = 1'b0;
-	parameter A_WE_INV = 1'b0;
-	parameter B_WE_INV = 1'b0;
-
-	// Output Register
-	parameter A_DO_REG = 1'b0;
-	parameter B_DO_REG = 1'b0;
-
-	// Error Checking and Correction
-	parameter A_ECC_EN  = 1'b0;
-	parameter B_ECC_EN  = 1'b0;
-endmodule
diff --git a/techlibs/gatemate/iob_map.v b/techlibs/gatemate/iob_map.v
index b73b4b9d2..7bbd47161 100644
--- a/techlibs/gatemate/iob_map.v
+++ b/techlibs/gatemate/iob_map.v
@@ -17,36 +17,6 @@
  *
  */
 
-module \$__inpad (input I, output Y);
-	CC_IBUF /*#(
-		.PIN_NAME("UNPLACED"),
-		.V_IO("UNDEFINED"),
-		.PULLUP(1'bx),
-		.PULLDOWN(1'bx),
-		.KEEPER(1'bx),
-		.SCHMITT_TRIGGER(1'bx),
-		.DELAY_IBF(4'bx),
-		.FF_IBF(1'bx)
-	)*/ _TECHMAP_REPLACE_ (
-		.I(I),
-		.Y(Y)
-	);
-endmodule
-
-module \$__outpad (input A, output O);
-	CC_OBUF /*#(
-		.PIN_NAME("UNPLACED"),
-		.V_IO("UNDEFINED"),
-		.SLEW("UNDEFINED"),
-		.DRIVE(1'bx),
-		.DELAY_OBF(4'bx),
-		.FF_OBF(1'bx)
-	)*/ _TECHMAP_REPLACE_ (
-		.A(A),
-		.O(O)
-	);
-endmodule
-
 module \$__toutpad (input A, input OE, output O);
 	CC_TOBUF /*#(
 		.PIN_NAME("UNPLACED"),
diff --git a/techlibs/gatemate/mul_map.v b/techlibs/gatemate/mul_map.v
index 8ab522815..123a1e631 100644
--- a/techlibs/gatemate/mul_map.v
+++ b/techlibs/gatemate/mul_map.v
@@ -17,8 +17,8 @@
  *
  */
 
-`define MAX(a,b) (a > b ? a : b)
-`define MIN(a,b) (a < b ? a : b)
+`define MAX(a,b) ((a) > (b) ? (a) : (b))
+`define MIN(a,b) ((a) < (b) ? (a) : (b))
 
 (* techmap_celltype = "$mul $__mul" *)
 module \$__MULMXN (A, B, Y);
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index 424d48b25..b570e1e2a 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -275,7 +275,7 @@ struct SynthGateMatePass : public ScriptPass
 			run("opt -undriven -fine");
 		}
 
-		if (check_label("map_addf", "(skip if '-noaddf')"))
+		if (check_label("map_gates"))
 		{
 			std::string techmap_args = "";
 			if (!noaddf) {
@@ -292,8 +292,8 @@ struct SynthGateMatePass : public ScriptPass
 		{
 			if (!noiopad) {
 				run("iopadmap -bits "
-					"-inpad $__inpad Y:I "
-					"-outpad $__outpad A:O "
+					"-inpad CC_IBUF Y:I "
+					"-outpad CC_OBUF A:O "
 					"-toutpad $__toutpad OE:A:O "
 					"-tinoutpad $__tinoutpad OE:Y:A:IO"
 				);
@@ -305,10 +305,7 @@ struct SynthGateMatePass : public ScriptPass
 		if (check_label("map_regs"))
 		{
 			run("opt_clean");
-			run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_???_ 0 "
-				"-cell $_DFFE_??_ 0 -cell $_DFFE_????_ 0 "
-				"-cell $_DLATCH_?_ x -cell $_DLATCH_???_ x"
-			);
+			run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
 			run("techmap -map +/gatemate/reg_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");