From: lkcl Date: Fri, 25 Dec 2020 01:43:48 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~926 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfe0fa917b49a251e23e9c61095ebfa0ca344dc9;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 98371c226..0b4d5c706 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -104,7 +104,7 @@ If all three registers are marked as Vector then the "traditional" predicated Ve Single Predication therefore provides several modes traditionally seen in Vector ISAs: * the predicate may be set as a single bit, the sources are scalar and the destination a vector: this gives VINSERT (VINDEX) behaviour. -* VSPLAT (result broadcasting) is provided by making the sources scalar and the destination a vector. +* VSPLAT (result broadcasting) is provided by making the sources scalar and the destination a vector, and having no predicate set or having multiple bits set. * VSELECT is provided by setting up (at least one of) the sources as a vector, using a single bit in olthe predicate, and the destination as a scalar. # Predicate "zeroing" mode