From: lkcl <lkcl@web>
Date: Sat, 2 Jan 2021 15:02:15 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~647
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cfea301337951b381d5d05a0beefa45b3ec1451d;p=libreriscv.git

---

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index b7890b95d..df1aeb5ae 100644
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -25,7 +25,7 @@ Loops, clearly, because if the setup of the shift registers does not precisely m
 
 # Swizzle Propagation
 
-Swizzle Contexts follow the same schedule except that there is a mask for specifying to which registers the swizzle is to be applied, and there is onlyy 17 bit suite to indicate the instructions to which the swizzle applies.
+Swizzle Contexts follow the same schedule except that there is a mask for specifying to which registers the swizzle is to be applied, and there is only 17 bit suite to indicate the instructions to which the swizzle applies.
 
 | 0.5|6.7 | 8.10| 11.14 | 15.31 |  name   |
 | -- | -- | --- | ----- | ----- | ------- |