From: lkcl Date: Tue, 22 Dec 2020 04:07:18 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1053 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d002e2e6e5fd875b5f36bef6eccd0e4b0ddd0a92;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index d5466f9e1..b000dd99f 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -134,41 +134,45 @@ variants. There are two categories: Single and Twin Predication. Due to space considerations further subdivision of Single Predication is based on whether the number of src operands is 2 or 3. - * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd). * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest) * `RM-2P-1S1D` Twin Predication (src=1, dest=1) * `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed) * `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update -## RM-1P-3S1D +## Common RM fields + +The following fields are common to all Remapped Encodings: + | Field Name | Field bits | Description | |------------|------------|----------------------------------------| | MASK\_KIND | `0` | Execution Mask Kind | | MASK | `1:3` | Execution Mask | | ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | +| SUBVL | `6:7` | Sub-vector length | +| MODE | `19:23` | changes Vector behaviour | + +Bits 9 to 18 are further decoded depending on RM category for the instruction. + +## RM-1P-3S1D + +| Field Name | Field bits | Description | +|------------|------------|----------------------------------------| | Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) | | Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | | Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | | Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) | | reserved | `16` | reserved | -| MODE | `19:23` | changes Vector behaviour | ## RM-1P-2S1D | Field Name | Field bits | Description | |------------|------------|-------------------------------------------| -| MASK\_KIND | `0` | Execution Mask Kind | -| MASK | `1:3` | Execution Mask | -| ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | | Rdest\_EXTRA3 | `8:10` | extends Rdest | | Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 | | Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 | | ELWIDTH_SRC | `17:18` | Element Width for Source | -| MODE | `19:23` | changes Vector behaviour | These are for 2 operand 1 dest instructions, such as `add RT, RA, RB`. However also included are unusual instructions with an implicit dest @@ -193,16 +197,10 @@ Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or in ## RM-2P-1S1D | Field Name | Field bits | Description | -|------------|------------|----------------------------| -| MASK_KIND | `0` | Execution Mask Kind | -| MASK | `1:3` | Execution Mask | -| ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | | Rdest_EXTRA3 | `8:10` | extends Rdest | | Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 | | MASK_SRC | `14:16` | Execution Mask for Source | | ELWIDTH_SRC | `17:18` | Element Width for Source | -| MODE | `19:23` | changes Vector behaviour | Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance or increased latency in some implementations due to lane-crossing. @@ -215,16 +213,11 @@ RM-2P-2S1D: | Field Name | Field bits | Description | |------------|------------|----------------------------| -| MASK_KIND | `0` | Execution Mask Kind | -| MASK | `1:3` | Execution Mask | -| ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | | Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) | | Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | | Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | | MASK_SRC | `14:16` | Execution Mask for Source | | ELWIDTH_SRC | `17:18` | Element Width for Source | -| MODE | `19:23` | changes Vector behaviour | Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2 is in bits 8:9, Rdest1_EXTRA2 in 10:11)