From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Mar 2021 23:11:11 +0000 (+0000)
Subject: remove sram4k wishbone bte/cti in litex interconnect
X-Git-Tag: convert-csv-opcode-to-binary~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0097592fecf8d278ac3fa505eca4f602c023455;p=soc.git

remove sram4k wishbone bte/cti in litex interconnect
---

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 189216e2..aa178c35 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -268,7 +268,8 @@ class LibreSoC(CPU):
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
         if "sram4k" in variant or variant == 'ls180':
             for i, sram in enumerate(srams):
-                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i,
+                                                     sram, simple=True))
 
         # and set ibus advanced tags to zero (disable)
         self.cpu_params['i_ibus__cti'] = 0