From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Sat, 11 Dec 2021 15:53:54 +0000 (+0100)
Subject: rtlil: Dump empty connections when whole module is selected.
X-Git-Tag: yosys-0.13~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d019b4e6810bce37bd3477bb365288cae2a572b2;p=yosys.git

rtlil: Dump empty connections when whole module is selected.

Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
---

diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc
index 68521d52d..1b11de5ec 100644
--- a/backends/rtlil/rtlil_backend.cc
+++ b/backends/rtlil/rtlil_backend.cc
@@ -358,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
 
 		bool first_conn_line = true;
 		for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
-			bool show_conn = !only_selected;
-			if (only_selected) {
+			bool show_conn = !only_selected || design->selected_whole_module(module->name);
+			if (!show_conn) {
 				RTLIL::SigSpec sigs = it->first;
 				sigs.append(it->second);
 				for (auto &c : sigs.chunks()) {