From: Kajol Jain <kajoljain797@gmail.com>
Date: Thu, 13 Jun 2019 08:42:02 +0000 (+0530)
Subject: arch-power: Add support for external interrupts
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d027e6bd5bed2cfa01c2e76fe76572859790ca95;p=gem5.git

arch-power: Add support for external interrupts

Change-Id: Ib6f0b12064498483b87d7030ca7551829766fe5b
Signed-off-by: Kajol Jain <kajoljain797@gmail.com>
---

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index c293ab1e0..80a5828b9 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -706,9 +706,12 @@ def makeLinuxPowerSystem(mem_mode, numCPUs=1, mdesc=None, cmdline=None):
     self.system_port = self.membus.slave
     self.intrctrl = IntrControl()
     if not cmdline:
-        cmdline = 'irqpoll lpj=1000000000'
+        cmdline = 'earlyprintk=ttyS0 console=ttyS0 irqpoll lpj=1000000000'
     self.boot_osflags = fillInCmdline(mdesc, cmdline)
-    self.kernel = binary('vmlinux')
+    #self.kernel = binary('vmlinux')
+    self.skiboot = binary('skiboot.elf');
+    self.kernel = binary('vmlinux');
+    self.initramfs = binary('initramfs.cpio');
     self.dtb_filename = binary('gem5-power9-fs.dtb')
     self.multi_thread = True;
     self._num_cpus = 2;
diff --git a/src/arch/power/PowerSystem.py b/src/arch/power/PowerSystem.py
index 67ab7d73a..eb1ab6d7d 100644
--- a/src/arch/power/PowerSystem.py
+++ b/src/arch/power/PowerSystem.py
@@ -43,6 +43,10 @@ class PowerSystem(System):
     cxx_header = 'arch/power/system.hh'
     dtb_filename = Param.String("",
         "File that contains the Device Tree Blob. Don't use DTB if empty.")
+    skiboot = Param.String("",
+            "File that contains the OPAL firmware.");
+    initramfs = Param.String("",
+            "File that contains the initramfs image");
     early_kernel_symbols = Param.Bool(False,
         "enable early kernel symbol tables before MMU")
 
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index d6c1a31b2..a4191b5ec 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -52,7 +52,8 @@ enum pcSet
     DataStoragePCSet = 0x300,
     InstrStoragePCSet = 0x400,
     PriDoorbellPCSet = 0xA00,
-    HypDoorbellPCSet = 0xe80
+    HypDoorbellPCSet = 0xe80,
+    DirectExternalPCSet = 0x500
 };
 
 extern long stdout_buf_addr;
@@ -153,6 +154,39 @@ class PowerInterrupt : public PowerFaultBase
     }
 };
 
+class DirectExternalInterrupt : public PowerInterrupt
+{
+  public:
+    DirectExternalInterrupt()
+    {
+    }
+    virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+                        StaticInst::nullStaticInstPtr)
+    {
+      printf("Direct External Interrupt invoked\n");
+      // Refer Power ISA Manual v3.0B Book-III, section 6.5.7.1
+      Lpcr lpcr = tc->readIntReg(INTREG_LPCR);
+
+      if (lpcr.lpes){
+        tc->setIntReg(INTREG_SRR0 , tc->instAddr());
+        PowerInterrupt::updateSRR1(tc);
+        PowerInterrupt::updateMsr(tc);
+        Msr msr =  tc->readIntReg(INTREG_MSR);
+        msr.ri = 0;
+        tc->setIntReg(INTREG_MSR, msr);
+      }
+      else{
+        tc->setIntReg(INTREG_HSRR0 , tc->instAddr());
+        PowerInterrupt::updateHSRR1(tc);
+        PowerInterrupt::updateMsr(tc);
+        Msr msr =  tc->readIntReg(INTREG_MSR);
+        msr.hv = 1;
+        tc->setIntReg(INTREG_MSR, msr);
+      }
+      tc->pcState(DirectExternalPCSet);
+    }
+};
+
 class PriDoorbellInterrupt : public PowerInterrupt
 {
   public:
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
index 81045d294..5dbe6c389 100644
--- a/src/arch/power/interrupts.hh
+++ b/src/arch/power/interrupts.hh
@@ -116,6 +116,8 @@ class Interrupts : public SimObject
          interrupts[Decrementer] = 1;
        if (msr.ee)
        {
+         if (interrupts[2] == 1)
+           return true;
          for (int i = 0; i < NumInterruptLevels; i++) {
              if (interrupts[i] == 1)
                return true;
@@ -142,6 +144,11 @@ class Interrupts : public SimObject
             clear(DirHypDoorbell,0);
             return std::make_shared<HypDoorbellInterrupt>();
         }
+        else if (interrupts[DirectExt]){
+            clear(DirectExt,0);
+            return std::make_shared<DirectExternalInterrupt>();
+        }
+
         else return NoFault;
     }
 
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 39c0ddef7..9e89d7419 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -698,6 +698,7 @@ decode PO default Unknown::unknown() {
                 0x378: mtmmcr0({{MMCR0 = Rs;}});
                 0x380: mtcfar({{ CFAR = Rs; }});
                 0x390: mttbl({{ TBL = Rs; }});
+                0x33c: mtspr({{ }});
                 0x3a0: mtamr({{AMR = Rs;}}, [ IsPrivileged ]);
                 0x3a1: mtiamr({{IAMR = Rs;}});
                 0x3a4: mtuamor({{UAMOR = Rs;}}, [ IsPrivileged ]);
diff --git a/src/arch/power/system.cc b/src/arch/power/system.cc
index db44eb58f..2acee2695 100644
--- a/src/arch/power/system.cc
+++ b/src/arch/power/system.cc
@@ -70,7 +70,8 @@ PowerSystem::initState()
                     (int)threadContexts.size());
 
     ThreadContext *tc = threadContexts[0];
-    tc->pcState(tc->getSystemPtr()->kernelEntry);
+    //tc->pcState(tc->getSystemPtr()->kernelEntry);
+    tc->pcState(0x10); // For skiboot
     //Sixty Four, little endian,Hypervisor bits are enabled.
     // IR and DR bits are disabled.
     Msr msr = 0x9000000000000001;
@@ -78,7 +79,8 @@ PowerSystem::initState()
     // This PVR is specific to power9
     // Setting TB register to 0
     tc->setIntReg(INTREG_TB , 0x0);
-    tc->setIntReg(INTREG_PVR , 0x004e1100);
+    //tc->setIntReg(INTREG_PVR , 0x004e1100);
+    tc->setIntReg(INTREG_PVR , 0x004e0200);
     tc->setIntReg(INTREG_MSR , msr);
     //ArgumentReg0 is initialized with 0xc00000 because in linux/system.cc
     //dtb is loaded at 0xc00000