From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Dec 2019 20:32:00 +0000 (-0800)
Subject: More stringent check for flop cells
X-Git-Tag: working-ls180~818^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d038cea3c7c5dd9f147c4da0e44de0e664df089f;p=yosys.git

More stringent check for flop cells
---

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 643cf0215..8dd238bc7 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -222,7 +222,8 @@ struct OptMergeWorker
 			return true;
 		}
 
-		if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
+		if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") ||
+					cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) {
 			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
 			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
@@ -324,7 +325,8 @@ struct OptMergeWorker
 							module->connect(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
 
-							if (cell->type.begins_with("$") && it.first == ID(Q)) {
+							if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") ||
+										cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) {
 								for (auto c : it.second.chunks()) {
 									auto jt = c.wire->attributes.find(ID(init));
 									if (jt == c.wire->attributes.end())