From: Luke Kenneth Casson Leighton Date: Mon, 3 Jun 2019 14:03:30 +0000 (+0100) Subject: add docstring for address match comparator X-Git-Tag: div_pipeline~1892 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0479b4c5d43d97d404722ef6bd7295b6eda0857;p=soc.git add docstring for address match comparator --- diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py index d7692b32..657f95b6 100644 --- a/src/scoreboard/addr_match.py +++ b/src/scoreboard/addr_match.py @@ -13,6 +13,12 @@ to do is cover the cases that are *definitely* matches (by checking 11 bits or so), and if a few opportunities for parallel LD/STs are missed because the top (or bottom) bits weren't checked, so what: all that happens is: the mis-matched addresses are LD/STd on single-cycles. Big Deal. + +However, if we wanted to enhance this algorithm (without using a CAM and +without using expensive comparators) probably the best way to do so would +be to turn the last 16 bits into a byte-level bitmap. LD/ST on a byte +would have 1 of the 16 bits set. LD/ST on a DWORD would have 8 of the 16 +bits set (offset if the LD/ST was misaligned). TODO. """ from nmigen.compat.sim import run_simulation