From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 21:51:17 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5261
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d04d7f431882b41fdc67053eb414c33506d2b016;p=libreriscv.git

update
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 930495748..18ae7b4cd 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -156,14 +156,15 @@
 \frame{\frametitle{Implementation Options}
 
  \begin{itemize}
-   \item Absolute minimum: Exceptions (if CSRs indicate "V", trap)
+   \item Absolute minimum: Exceptions: if CSRs indicate "V", trap.\\
+         (Requires as absolute minimum that CSRs be in H/W)
    \item Hardware loop, single-instruction issue\\
 		 (Do / Don't send through predication to ALU)
    \item Hardware loop, parallel (multi-instruction) issue\\
    		 (Do / Don't send through predication to ALU)
    \item Hardware loop, full parallel ALU (not recommended)
   \end{itemize}
-  Notes:\vspace{6pt}
+  Notes:\vspace{4pt}
   \begin{itemize}
    \item 4 (or more?) options above may be deployed on per-op basis
    \item SIMD always sends predication bits through to ALU