From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 19:18:18 +0000 (+0100)
Subject: add ShiftRot test case (works only because CRs are not tested)
X-Git-Tag: div_pipeline~580
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d04e0af11d6281ee2bbf5742b69e244094202d59;p=soc.git

add ShiftRot test case (works only because CRs are not tested)
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 22bd3bc1..82d6d52b 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -16,6 +16,7 @@ from soc.experiment.compalu_multi import find_ok # hack
 # test with ALU data and Logical data
 from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase
 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
+from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 
 
 def set_cu_input(cu, idx, data):
@@ -218,6 +219,7 @@ class TestRunner(FHDLTestCase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
+    suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     suite.addTest(TestRunner(LogicalTestCase.test_data))
     suite.addTest(TestRunner(ALUTestCase.test_data))