From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Sep 2021 22:47:32 +0000 (+0100)
Subject: add in a stack of comments for identifying match-points with StateRunner
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0512df768fec45afe10a553b0f7564ae50db3f8;p=soc.git

add in a stack of comments for identifying match-points with StateRunner
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 69b1ccfc..99ca54c3 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -290,6 +290,9 @@ class TestRunner(FHDLTestCase):
                              svp64=self.svp64,
                              mmu=self.microwatt_mmu,
                              reg_wid=64)
+
+        ###### SETUP PHASE #######
+
         if self.run_hdl:
             #hard_reset = Signal(reset_less=True)
             issuer = TestIssuerInternal(pspec)
@@ -319,6 +322,8 @@ class TestRunner(FHDLTestCase):
 
         def process():
 
+            ###### PREPARATION PHASE AT START OF RUNNING #######
+
             if self.run_hdl:
                 # start in stopped
                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
@@ -328,19 +333,22 @@ class TestRunner(FHDLTestCase):
 
             for test in self.test_data:
 
-                if self.run_hdl:
-                    # set up bigendian (TODO: don't do this, use MSR)
-                    yield issuer.core_bigendian_i.eq(bigendian)
-                    yield Settle()
+                with self.subTest(test.name):
 
-                    yield
-                    yield
-                    yield
-                    yield
+                    ###### PREPARATION PHASE AT START OF TEST #######
 
-                print(test.name)
-                program = test.program
-                with self.subTest(test.name):
+                    if self.run_hdl:
+                        # set up bigendian (TODO: don't do this, use MSR)
+                        yield issuer.core_bigendian_i.eq(bigendian)
+                        yield Settle()
+
+                        yield
+                        yield
+                        yield
+                        yield
+
+                    print(test.name)
+                    program = test.program
                     print("regs", test.regs)
                     print("sprs", test.sprs)
                     print("cr", test.cr)
@@ -351,6 +359,8 @@ class TestRunner(FHDLTestCase):
                     insncode = program.assembly.splitlines()
                     instructions = list(zip(gen, insncode))
 
+                    ###### RUNNING OF EACH TEST #######
+
                     # Run two tests (TODO, move these to functions)
                     # * first the Simulator, collate a batch of results
                     # * then the HDL, likewise
@@ -377,6 +387,8 @@ class TestRunner(FHDLTestCase):
                                                           instructions, gen,
                                                           insncode)
 
+                    ###### COMPARING THE TESTS #######
+
                     ###############
                     # 3. Compare
                     ###############
@@ -417,6 +429,8 @@ class TestRunner(FHDLTestCase):
                         self.assertTrue(len(hdl_states) == len(sim_states),
                                     "number of instructions run not the same")
 
+                ###### END OF A TEST #######
+
                 if self.run_hdl:
                     # stop at end
                     yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)