From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Nov 2021 15:21:15 +0000 (+0000)
Subject: add code-comments, link to in-order core
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0699a862f265f26050409cb00b1854db5ea7f6f;p=soc.git

add code-comments, link to in-order core
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 9be51cc3..de1d2d68 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -17,6 +17,8 @@ the brain-dead part of this module is that even though there is no
 conflict of access, regfile read/write hazards are *not* analysed,
 and consequently it is safer to wait for the Function Unit to complete
 before allowing a new instruction to proceed.
+(update: actually this is being added now:
+https://bugs.libre-soc.org/show_bug.cgi?id=737)
 """
 
 from nmigen import (Elaboratable, Module, Signal, ResetSignal, Cat, Mux,