From: whitequark <whitequark@whitequark.org>
Date: Wed, 15 Jul 2020 04:09:58 +0000 (+0000)
Subject: back.rtlil: fix guard for division by zero.
X-Git-Tag: 24jan2021_ls180~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d06add0aab5abb386a6d07a0430ca7a7a8373fe4;p=nmigen.git

back.rtlil: fix guard for division by zero.

Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 3838101..f772778 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -558,7 +558,7 @@ class _RHSValueCompiler(_ValueCompiler):
             self.s.rtlil.cell("$mux", ports={
                 "\\A": divmod_res,
                 "\\B": self(ast.Const(0, ast.Shape(res_bits, res_sign))),
-                "\\S": self(lhs == 0),
+                "\\S": self(rhs == 0),
                 "\\Y": res,
             }, params={
                 "WIDTH": res_bits