From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Dec 2023 19:28:29 +0000 (+0000)
Subject: bug #1183: add test function sv_cmpi
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d07178739efa394256bc0cba4a78fa61e1c04c74;p=openpower-isa.git

bug #1183: add test function sv_cmpi

based on https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
index 666db4d2..1fc44770 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
@@ -9,7 +9,28 @@ from openpower.simulator.program import Program
 from openpower.insndb.asm import SVP64Asm
 
 
-class DecoderTestCase(FHDLTestCase):
+def cmpd(x, y):
+    class CRfield: object
+    CRf = CRfield()
+    CRf.lt = x < y
+    CRf.gt = x > y
+    CRf.eq = x == y
+    return CRf
+
+
+# example sv.cmpi/ff=lt 0, 1, *10, 5
+# see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
+def sv_cmpi(gpr, CR, vl, ra, si):
+    i = 0
+    while i < VL:
+        CR[idx] = cmpd(gpr[rz + i], si)
+        if CR[idx].lt:
+            break
+        i += 1
+    return i # new VL
+
+
+class DDFFirstTestCase(FHDLTestCase):
 
     def _check_regs(self, sim, expected):
         for i in range(32):