From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 7 Feb 2020 14:29:32 +0000 (-0500)
Subject: modify reorder_bits to copy the MSB of the partition to each bit
X-Git-Tag: ls180-24jan2020~244
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d07c689dc09ada1f3b408dcff9858b514a42dc80;p=ieee754fpu.git

modify reorder_bits to copy the MSB of the partition to each bit

Previously, it would move the MSB to the LSB, and set the rest of the
bits to 0.
---

diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py
index 7207c0f4..9772522a 100644
--- a/src/ieee754/part_cmp/eq_gt_ge.py
+++ b/src/ieee754/part_cmp/eq_gt_ge.py
@@ -53,7 +53,6 @@ class PartitionedEqGtGe(Elaboratable):
         m.submodules.gtc = gtc = GTCombiner(self.mwidth)
 
         m.submodules.reorder = reorder = ReorderResults(self.mwidth)
-        m.submodules.ripple = ripple = RippleLSB(self.mwidth)
 
         # make a series of "eqs" and "gts", splitting a and b into
         # partition chunks
@@ -99,10 +98,8 @@ class PartitionedEqGtGe(Elaboratable):
 
         comb += reorder.results_in.eq(results)
         comb += reorder.gates.eq(self.partition_points.as_sig())
-        comb += ripple.results_in.eq(reorder.output)
-        comb += ripple.gates.eq(self.partition_points.as_sig())
 
-        comb += self.output.eq(ripple.output)
+        comb += self.output.eq(reorder.output)
 
         return m
 
diff --git a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
index 8d223746..13c42343 100644
--- a/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
+++ b/src/ieee754/part_cmp/formal/proof_eq_gt_ge.py
@@ -58,21 +58,21 @@ class EqualsDriver(Elaboratable):
             with m.Switch(gates):
                 with m.Case(0b00):
                     comb += Assert(out[0] == (a == b))
-                    comb += Assert(out[1] == 0)
-                    comb += Assert(out[2] == 0)
+                    comb += Assert(out[1] == out[0])
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b01):
                     comb += Assert(out[0] == (a_intervals[0] == b_intervals[0]))
                     comb += Assert(out[1] == ((a_intervals[1] == \
                                     b_intervals[1]) &
                                               (a_intervals[2] == \
                                     b_intervals[2])))
-                    comb += Assert(out[2] == 0)
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b10):
                     comb += Assert(out[0] == ((a_intervals[0] == \
                                     b_intervals[0]) &
                                               (a_intervals[1] == \
                                     b_intervals[1])))
-                    comb += Assert(out[1] == 0)
+                    comb += Assert(out[1] == out[0])
                     comb += Assert(out[2] == (a_intervals[2] == b_intervals[2]))
                 with m.Case(0b11):
                     for i in range(mwidth-1):
@@ -81,17 +81,19 @@ class EqualsDriver(Elaboratable):
         with m.If(opcode == 0b01):
             with m.Switch(gates):
                 with m.Case(0b00):
-                    comb += Assert(out == (a > b))
+                    comb += Assert(out[0] == (a > b))
+                    comb += Assert(out[1] == out[0])
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b01):
                     comb += Assert(out[0] == (a_intervals[0] > b_intervals[0]))
 
                     comb += Assert(out[1] == (Cat(*a_intervals[1:3]) > \
                                               Cat(*b_intervals[1:3])))
-                    comb += Assert(out[2] == 0)
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b10):
                     comb += Assert(out[0] == (Cat(*a_intervals[0:2]) > \
                                               Cat(*b_intervals[0:2])))
-                    comb += Assert(out[1] == 0)
+                    comb += Assert(out[1] == out[0])
                     comb += Assert(out[2] == (a_intervals[2] > b_intervals[2]))
                 with m.Case(0b11):
                     for i in range(mwidth-1):
@@ -100,17 +102,19 @@ class EqualsDriver(Elaboratable):
         with m.If(opcode == 0b10):
             with m.Switch(gates):
                 with m.Case(0b00):
-                    comb += Assert(out == (a >= b))
+                    comb += Assert(out[0] == (a >= b))
+                    comb += Assert(out[1] == out[0])
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b01):
                     comb += Assert(out[0] == (a_intervals[0] >= b_intervals[0]))
 
                     comb += Assert(out[1] == (Cat(*a_intervals[1:3]) >= \
                                               Cat(*b_intervals[1:3])))
-                    comb += Assert(out[2] == 0)
+                    comb += Assert(out[2] == out[1])
                 with m.Case(0b10):
                     comb += Assert(out[0] == (Cat(*a_intervals[0:2]) >= \
                                               Cat(*b_intervals[0:2])))
-                    comb += Assert(out[1] == 0)
+                    comb += Assert(out[1] == out[0])
                     comb += Assert(out[2] == (a_intervals[2] >= b_intervals[2]))
                 with m.Case(0b11):
                     for i in range(mwidth-1):
diff --git a/src/ieee754/part_cmp/reorder_results.py b/src/ieee754/part_cmp/reorder_results.py
index 577f1702..41c64652 100644
--- a/src/ieee754/part_cmp/reorder_results.py
+++ b/src/ieee754/part_cmp/reorder_results.py
@@ -23,7 +23,7 @@ class ReorderResults(Elaboratable):
         for i in range(width-2, -1, -1):  # counts down from width-1 to 0
             cur = Signal()
             comb += cur.eq(current_result)
-            comb += self.output[i+1].eq(cur & self.gates[i])
+            comb += self.output[i+1].eq(cur)
             current_result = Mux(self.gates[i], self.results_in[i], cur)
 
             comb += self.output[0].eq(current_result)