From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 31 Oct 2018 14:36:53 +0000 (+0100)
Subject: Fix sf2 LUT interface
X-Git-Tag: yosys-0.9~427^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d084fb4c3f389b99c08909666d8e953017cb7656;p=yosys.git

Fix sf2 LUT interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v
index 7585323a8..5b8888294 100644
--- a/techlibs/sf2/cells_map.v
+++ b/techlibs/sf2/cells_map.v
@@ -50,16 +50,16 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]));
+      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
     end else
     if (WIDTH == 2) begin
-      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]));
+      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
     end else
     if (WIDTH == 3) begin
-      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]));
+      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
     end else
     if (WIDTH == 4) begin
-      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 89b8c55fd..b03b2c750 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -37,39 +37,39 @@ module SLE (
 endmodule
 
 module CFG1 (
-	output O,
+	output Y,
 	input A
 );
 	parameter [1:0] INIT = 2'h0;
-	assign O = INIT >> A;
+	assign Y = INIT >> A;
 endmodule
 
 module CFG2 (
-	output O,
+	output Y,
 	input A,
 	input B
 );
 	parameter [3:0] INIT = 4'h0;
-	assign O = INIT >> {B, A};
+	assign Y = INIT >> {B, A};
 endmodule
 
 module CFG3 (
-	output O,
+	output Y,
 	input A,
 	input B,
 	input C
 );
 	parameter [7:0] INIT = 8'h0;
-	assign O = INIT >> {C, B, A};
+	assign Y = INIT >> {C, B, A};
 endmodule
 
 module CFG4 (
-	output O,
+	output Y,
 	input A,
 	input B,
 	input C,
 	input D
 );
 	parameter [15:0] INIT = 16'h0;
-	assign O = INIT >> {D, C, B, A};
+	assign Y = INIT >> {D, C, B, A};
 endmodule