From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 21:06:07 +0000 (-0700)
Subject: SigSpec::extract to allow negative length
X-Git-Tag: working-ls180~1039^2~359
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d086dfb5b0d4f1f8e60a9e32d874a1f94cf73c66;p=yosys.git

SigSpec::extract to allow negative length
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ebb6f5bf6..6f5082138 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
 {
 	unpack();
 	cover("kernel.rtlil.sigspec.extract_pos");
-	return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
+	return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1);
 }
 
 void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)