From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 12:22:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~509
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d08c8125ee08e0974c0b43570c16c774aff7954e;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 4187eff1d..aeb7b7718 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -159,7 +159,8 @@ Pseudocode for Horizontal-First Mode:
         if predicate[srcstep]:
             # get SVP64 extended CR field 0..127
             SVCRf = SVP64EXTRA(BI>>2)
-            CR{SVCRf+srcstep} = CRbits
+            if Rc = 1 then # CR0 Vectorised
+                CR{0+srcstep} = CRbits
             testbit = CRbits[BI & 0b11]
             # testbit = CR[BI+32+srcstep*4]
         else if not SVRMmode.sz:
@@ -197,7 +198,8 @@ Pseudocode for Vertical-First Mode:
     if predicate[srcstep]:
         # get SVP64 extended CR field 0..127
         SVCRf = SVP64EXTRA(BI>>2)
-        CR{SVCRf+srcstep} = CRbits
+        if Rc = 1 then # CR0 vectorised
+            CR{0+srcstep} = CRbits
         testbit = CRbits[BI & 0b11]
     else if not SVRMmode.sz:
         SVSTATE.srcstep = new_srcstep