From: Jordan Justen <jordan.l.justen@intel.com>
Date: Thu, 14 Feb 2019 10:26:53 +0000 (-0800)
Subject: iris: Emit default L3 config for the render pipeline
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0996d5fab6d0ef2ad6e046c2178cfc3488567e7;p=mesa.git

iris: Emit default L3 config for the render pipeline

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index bd222db4843..698c1cb9f62 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -617,6 +617,41 @@ init_state_base_address(struct iris_batch *batch)
    }
 }
 
+static void
+iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
+                    bool has_slm, bool wants_dc_cache)
+{
+   uint32_t reg_val;
+   iris_pack_state(GENX(L3CNTLREG), &reg_val, reg) {
+      reg.SLMEnable = has_slm;
+#if GEN_GEN == 11
+      /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+       * in L3CNTLREG register. The default setting of the bit is not the
+       * desirable behavior.
+       */
+      reg.ErrorDetectionBehaviorControl = true;
+#endif
+      reg.URBAllocation = cfg->n[GEN_L3P_URB];
+      reg.ROAllocation = cfg->n[GEN_L3P_RO];
+      reg.DCAllocation = cfg->n[GEN_L3P_DC];
+      reg.AllAllocation = cfg->n[GEN_L3P_ALL];
+   }
+   iris_emit_lri(batch, L3CNTLREG, reg_val);
+}
+
+static void
+iris_emit_default_l3_config(struct iris_batch *batch,
+                            const struct gen_device_info *devinfo,
+                            bool compute)
+{
+   bool wants_dc_cache = true;
+   bool has_slm = compute;
+   const struct gen_l3_weights w =
+      gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
+   const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
+   iris_emit_l3_config(batch, cfg, has_slm, wants_dc_cache);
+}
+
 /**
  * Upload the initial GPU state for a render context.
  *
@@ -634,6 +669,8 @@ iris_init_render_context(struct iris_screen *screen,
 
    emit_pipeline_select(batch, _3D);
 
+   iris_emit_default_l3_config(batch, devinfo, false);
+
    init_state_base_address(batch);
 
 #if GEN_GEN >= 9
@@ -728,29 +765,7 @@ iris_init_compute_context(struct iris_screen *screen,
 
    emit_pipeline_select(batch, GPGPU);
 
-   const bool has_slm = true;
-   const bool wants_dc_cache = true;
-
-   const struct gen_l3_weights w =
-      gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
-   const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
-
-   uint32_t reg_val;
-   iris_pack_state(GENX(L3CNTLREG), &reg_val, reg) {
-      reg.SLMEnable = has_slm;
-#if GEN_GEN == 11
-      /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
-       * in L3CNTLREG register. The default setting of the bit is not the
-       * desirable behavior.
-       */
-      reg.ErrorDetectionBehaviorControl = true;
-#endif
-      reg.URBAllocation = cfg->n[GEN_L3P_URB];
-      reg.ROAllocation = cfg->n[GEN_L3P_RO];
-      reg.DCAllocation = cfg->n[GEN_L3P_DC];
-      reg.AllAllocation = cfg->n[GEN_L3P_ALL];
-   }
-   iris_emit_lri(batch, L3CNTLREG, reg_val);
+   iris_emit_default_l3_config(batch, devinfo, true);
 
    init_state_base_address(batch);