From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Sep 2018 01:18:19 +0000 (+0100)
Subject: revert addition of svsetvl as an actual opcode, add mvl CSR instead
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0a1ad054793d1e39d1dc9c2f3b61235c318223d;p=riscv-isa-sim.git

revert addition of svsetvl as an actual opcode, add mvl CSR instead

this is less than ideal but better than having to add new opcodes
---

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 6ec2564..02b22a5 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -893,40 +893,9 @@
 #define CSR_MHPMEVENT30 0x33e
 #define CSR_MHPMEVENT31 0x33f
 #define CSR_SVGETVL 0xcf0
-#define CSR_SVSETVL_BASE 0x4e0
-#define CSR_SVSETVL_MASK 0x1f
-#define CSR_SVSETVL_R0 0x4e0
-#define CSR_SVSETVL_R1 0x4e1
-#define CSR_SVSETVL_R2 0x4e2
-#define CSR_SVSETVL_R3 0x4e3
-#define CSR_SVSETVL_R4 0x4e4
-#define CSR_SVSETVL_R5 0x4e5
-#define CSR_SVSETVL_R6 0x4e6
-#define CSR_SVSETVL_R7 0x4e7
-#define CSR_SVSETVL_R8 0x4e8
-#define CSR_SVSETVL_R9 0x4e9
-#define CSR_SVSETVL_R10 0x4ea
-#define CSR_SVSETVL_R11 0x4eb
-#define CSR_SVSETVL_R12 0x4ec
-#define CSR_SVSETVL_R13 0x4ed
-#define CSR_SVSETVL_R14 0x4ee
-#define CSR_SVSETVL_R15 0x4ef
-#define CSR_SVSETVL_R16 0x4f0
-#define CSR_SVSETVL_R17 0x4f1
-#define CSR_SVSETVL_R18 0x4f2
-#define CSR_SVSETVL_R19 0x4f3
-#define CSR_SVSETVL_R20 0x4f4
-#define CSR_SVSETVL_R21 0x4f5
-#define CSR_SVSETVL_R22 0x4f6
-#define CSR_SVSETVL_R23 0x4f7
-#define CSR_SVSETVL_R24 0x4f8
-#define CSR_SVSETVL_R25 0x4f9
-#define CSR_SVSETVL_R26 0x4fa
-#define CSR_SVSETVL_R27 0x4fb
-#define CSR_SVSETVL_R28 0x4fc
-#define CSR_SVSETVL_R29 0x4fd
-#define CSR_SVSETVL_R30 0x4fe
-#define CSR_SVSETVL_R31 0x4ff
+#define CSR_SVSETVL 0xcf1
+#define CSR_SVGETMVL 0xcf2
+#define CSR_SVSETMVL 0xcf3
 #define CSR_MVENDORID 0xf11
 #define CSR_MARCHID 0xf12
 #define CSR_MIMPID 0xf13
@@ -1275,6 +1244,10 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 #endif
 #ifdef DECLARE_CSR
+DECLARE_CSR(svsetvl, CSR_SVSETVL)
+DECLARE_CSR(svgetvl, CSR_SVGETVL)
+DECLARE_CSR(svsetmvl, CSR_SVSETMVL)
+DECLARE_CSR(svgetmvl, CSR_SVGETMVL)
 DECLARE_CSR(fflags, CSR_FFLAGS)
 DECLARE_CSR(frm, CSR_FRM)
 DECLARE_CSR(fcsr, CSR_FCSR)
diff --git a/riscv/insns/csrrw.h b/riscv/insns/csrrw.h
index e45420b..b7911f5 100644
--- a/riscv/insns/csrrw.h
+++ b/riscv/insns/csrrw.h
@@ -1,5 +1,18 @@
 int csr = validate_csr(insn.csr(), true);
+#ifdef SPIKE_SIMPLEV
+reg_t old;
+if (csr != CSR_SVSETVL)
+{
+    old = p->get_csr(csr);
+}
+p->set_csr(csr, RS1);
+if (csr == CSR_SVSETVL)
+{
+    old = p->get_csr(csr);
+}
+#else
 reg_t old = p->get_csr(csr);
 p->set_csr(csr, RS1);
+#endif
 WRITE_RD(sext_xlen(old));
 serialize();
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 237eedc..603aaf6 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -333,29 +333,15 @@ void processor_t::set_csr(int which, reg_t val)
   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
                        | ((ext != NULL) << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
-#ifdef SPIKE_SIMPLEV
-  // SV SETVL includes the target register in the lower bits (0-31)
-  uint64_t sv_target = 0;
-  uint64_t sv_which = which & ~CSR_SVSETVL_MASK;
-  if (sv_which == CSR_SVSETVL_BASE)
-  {
-    sv_target = which & CSR_SVSETVL_MASK;
-    which = sv_which;
-  }
-#endif
   switch (which)
   {
 #ifdef SPIKE_SIMPLEV
-    case CSR_SVSETVL_BASE:
-      val = std::min((uint64_t)63,
-                 std::min((uint64_t)val,
-                           state.XPR[sv_target]));
-      // use CSR_SVSETVL_R0 to set VL to zero without side-effects
-      if (sv_target != 0)
-      {
-          state.XPR.write(sv_target, val);
-      }
-      state.vl = val;
+    case CSR_SVSETMVL:
+      state.mvl = std::min(val, (uint64_t)63); // limited to XLEN width
+      break;
+    case CSR_SVSETVL:
+      state.vl = std::min(state.mvl, state.XPR[val]);
+      state.XPR.write(val, state.vl);
       break;
 #endif
     case CSR_FFLAGS:
@@ -582,8 +568,10 @@ reg_t processor_t::get_csr(int which)
   switch (which)
   {
 #ifdef SPIKE_SIMPLEV
-    case CSR_SVGETV:
+    case CSR_SVGETVL:
       return state.vl;
+    case CSR_SVGETMVL:
+      return state.mvl;
 #endif
     case CSR_FFLAGS:
       require_fp;
diff --git a/riscv/processor.h b/riscv/processor.h
index 13466c6..e2c63c8 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -125,6 +125,7 @@ struct state_t
 
 #ifdef SPIKE_SIMPLEV
   uint64_t vl;
+  uint64_t mvl;
 #endif
 
   uint32_t fflags;