From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Wed, 6 Nov 2013 05:01:34 +0000 (-0800)
Subject: correctly trap when SR_EA is disabled
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be;p=riscv-isa-sim.git

correctly trap when SR_EA is disabled
---

diff --git a/hwacha/hwacha.cc b/hwacha/hwacha.cc
index 398fa28..8caf91e 100644
--- a/hwacha/hwacha.cc
+++ b/hwacha/hwacha.cc
@@ -31,6 +31,7 @@ void hwacha_t::reset()
 
 static reg_t custom(processor_t* p, insn_t insn, reg_t pc)
 {
+  require_accelerator;
   hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
   bool matched = false;
   reg_t npc = -1;
diff --git a/riscv/decode.h b/riscv/decode.h
index 7cf7eac..3fc2be7 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -145,6 +145,7 @@ private:
 #else
 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
 #endif
+#define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
 
 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index 7988c01..e51aee5 100644
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -5,6 +5,7 @@
 #define customX(n) \
   static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
   { \
+    require_accelerator; \
     rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \
     rocc_insn_union_t u; \
     u.i = insn; \
diff --git a/riscv/trap.h b/riscv/trap.h
index 9a1a2f9..bd7e0ee 100644
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -54,5 +54,6 @@ DECLARE_MEM_TRAP(8, load_address_misaligned)
 DECLARE_MEM_TRAP(9, store_address_misaligned)
 DECLARE_MEM_TRAP(10, load_access_fault)
 DECLARE_MEM_TRAP(11, store_access_fault)
+DECLARE_TRAP(12, accelerator_disabled)
 
 #endif