From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Thu, 14 Apr 2016 06:13:51 +0000 (-0700)
Subject: Added GP_SHREG cell
X-Git-Tag: yosys-0.7~256^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0aaf8d2621fd75b968700ec4cb8dd6acf568737;p=yosys.git

Added GP_SHREG cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1860970d2..554e2e13f 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -227,6 +227,29 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI
 	
 endmodule
 
+module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
+
+	parameter OUTA_DELAY = 1;
+	parameter OUTA_INVERT = 0;
+	parameter OUTB_DELAY = 1;
+	
+	reg[15:0] shreg = 0;
+	
+	always @(posedge clk, negedge RSTN) begin
+		
+		if(!nRST)
+			shreg = 0;
+		
+		else
+			shreg <= {shreg[14:0], IN};
+		
+	end
+	
+	assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
+	assign OUTB = shreg[OUTB_DELAY - 1];
+
+endmodule
+
 //keep constraint needed to prevent optimization since we have no outputs
 (* keep *)
 module GP_SYSRESET(input RST);