From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2019 13:51:35 +0000 (+0100)
Subject: Add "hdlname" attribute
X-Git-Tag: yosys-0.9~218
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc;p=yosys.git

Add "hdlname" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/README.md b/README.md
index c5cd47707..4048ecbc7 100644
--- a/README.md
+++ b/README.md
@@ -315,6 +315,9 @@ Verilog Attributes and non-standard features
 - The ``dynports'' attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 
+- The ``hdlname'' attribute is used by some passes to document the original
+  (HDL) name of a module when renaming a module.
+
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.
diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index c88ecd82e..e6154e94f 100644
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -87,6 +87,8 @@ struct UniquifyPass : public Pass {
 					smod->name = newname;
 					cell->type = newname;
 					smod->set_bool_attribute("\\unique");
+					if (smod->attributes.count("\\hdlname") == 0)
+						smod->attributes["\\hdlname"] = string(log_id(tmod->name));
 					design->add(smod);
 
 					did_something = true;