From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 13 Jun 2021 14:31:30 +0000 (+0100)
Subject: update ics2021 slides
X-Git-Tag: DRAFT_SVP64_0_1~754
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0bb9d95aa5c9b0ad202f71cc1f197516bb0a935;p=libreriscv.git

update ics2021 slides
---

diff --git a/conferences/ics2021/ics2021_svp64.tex b/conferences/ics2021/ics2021_svp64.tex
index 7a26b5426..27a4a83c1 100644
--- a/conferences/ics2021/ics2021_svp64.tex
+++ b/conferences/ics2021/ics2021_svp64.tex
@@ -98,20 +98,17 @@
 \frame{\frametitle{The summary on SVP64}
 
  \begin{itemize}
+   \item Specification: https://libre-soc.org/openpower/sv/svp64/
    \item SVP64 is similar to Intel x86 "REP" instruction\\
    		 "please repeat the following instruction N times"\\
    		 (but add some extra "stuff" in the process)
-   		    		  \vspace{2pt}
    \item Uses the Cray-style "setvl" instruction\\
    		 (Cray-I, NEC SX-Aurora, RISC-V RVV)\\
-   		  \vspace{2pt}
    \item Unlike "REP" there is additional "Vector context":\\
    		 Predication, Twin-predication, Element-width Overrides,
    		 Map-reduce, Iteration, Saturation and more.
-   		  \vspace{2pt}
    \item Just like "REP", none of this requires extra instructions!\\
    		 (except setvl and the "REP"-like prefix itself)\\
-   		  \vspace{2pt}
    \item "SIMD Considered Harmful" principle applies equally
    		 to RISC-V Vectors (190+ instructions on top of RV64GC's 80)\\
    		 \em{RVV more than doubles the number of RISC-V instructions}.