From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 19:43:59 +0000 (-0700)
Subject: Extend sign extension tests
X-Git-Tag: yosys-0.9~58^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0bbf9e4d4a508179b55a0cc7793d984f3318f7c;p=yosys.git

Extend sign extension tests
---

diff --git a/tests/various/signext.ys b/tests/various/signext.ys
index ae44a0e06..0c8d671e7 100644
--- a/tests/various/signext.ys
+++ b/tests/various/signext.ys
@@ -1,7 +1,13 @@
 
 read_verilog -formal <<EOT
-module gate(input clk, output [1:0] o);
-assign o = 1'bx;
+module gate(input clk, output [32:0] o, p, q, r, s, t, u);
+assign o = 'bx;
+assign p = 1'bx;
+assign q = 'bz;
+assign r = 1'bz;
+assign s = 1'b0;
+assign t = 'b1;
+assign u = -'sb1;
 endmodule
 EOT
 
@@ -10,8 +16,14 @@ proc
 ## Equivalence checking
 
 read_verilog -formal <<EOT
-module gold(input clk, output [1:0] o);
-assign o = 2'bxx;
+module gold(input clk, output [32:0] o, p, q, r, s, t, u);
+assign o = {33{1'bx}};
+assign p = {{32{1'b0}}, 1'bx};
+assign q = {33{1'bz}};
+assign r = {{32{1'b0}}, 1'bz};
+assign s = {33{1'b0}};
+assign t = {{32{1'b0}}, 1'b1};
+assign u = {33{1'b1}};
 endmodule
 EOT