From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 11 Mar 2019 12:32:48 +0000 (+0000)
Subject: return mid as part of ports
X-Git-Tag: ls180-24jan2020~1693
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0c5c2d71fb122797f6a02a6da30c404c0ff90b9;p=ieee754fpu.git

return mid as part of ports
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 05736f9c..74ce502d 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -118,7 +118,7 @@ class InputGroup:
         for i in range(self.num_rows):
             inop = self.rs[i]
             res += inop.in_op + [inop.stb]
-        return self.out_op.ports() + res #+ [self.ack + self.stb]
+        return self.out_op.ports() + res + [self.mid]
 
 
 class FPGetOpMod: