From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 Jan 2020 01:33:47 +0000 (-0800)
Subject: ifndef __ICARUS__ -> ifdef YOSYS
X-Git-Tag: working-ls180~883^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0d3ab8f676cd355d74cb7b7f71fc5bfca0719a2;p=yosys.git

ifndef __ICARUS__ -> ifdef YOSYS
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d705451fe..2947fe692 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2160,13 +2160,13 @@ module DSP48E1 (
     output reg [3:0] CARRYOUT,
     output reg MULTSIGNOUT,
     output OVERFLOW,
-`ifndef __ICARUS__
+`ifdef YOSYS
     (* abc9_arrival = \DSP48E1.P_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
 `endif
     output reg signed [47:0] P,
     output reg PATTERNBDETECT,
     output reg PATTERNDETECT,
-`ifndef __ICARUS__
+`ifdef YOSYS
     (* abc9_arrival = \DSP48E1.PCOUT_arrival (USE_MULT, USE_DPORT, AREG, ADREG, BREG, CREG, DREG, MREG, PREG) *)
 `endif
     output [47:0] PCOUT,