From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Sep 2019 20:26:34 +0000 (-0700)
Subject: Move unextend initialisation later
X-Git-Tag: working-ls180~1039^2~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0dbbc26054d1cd7b8766e2d996196e246216e8c;p=yosys.git

Move unextend initialisation later
---

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 19fe48bba..37674efea 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -3,7 +3,15 @@ pattern xilinx_dsp_cascadeP
 udata <std::function<SigSpec(const SigSpec&)>> unextend
 state <SigSpec> sigC
 
-code
+match dsp_pcin
+	select dsp_pcin->type.in(\DSP48E1)
+	select !param(dsp_pcin, \CREG, State::S1).as_bool()
+	select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
+	select nusers(port(dsp_pcin, \C, SigSpec())) > 1
+	select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0
+endmatch
+
+code sigC
 	unextend = [](const SigSpec &sig) {
 		int i;
 		for (i = GetSize(sig)-1; i > 0; i--)
@@ -14,17 +22,6 @@ code
 			++i;
 		return sig.extract(0, i);
 	};
-endcode
-
-match dsp_pcin
-	select dsp_pcin->type.in(\DSP48E1)
-	select !param(dsp_pcin, \CREG, State::S1).as_bool()
-	select port(dsp_pcin, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
-	select nusers(port(dsp_pcin, \C, SigSpec())) > 1
-	select nusers(port(dsp_pcin, \PCIN, SigSpec())) == 0
-endmatch
-
-code sigC
 	sigC = unextend(port(dsp_pcin, \C));
 endcode