From: lkcl <lkcl@web>
Date: Sat, 2 Jul 2022 10:16:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1412
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0dfbc6adeb6f2fd874e4ee4ea1214baebbf19b7;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index f0ea713ae..6590db9bd 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -69,7 +69,8 @@ than, as in RVV, allowing the hardware to set VL to an arbitrary value
 
 Also available is the option to set VL from CTR (`VL = MIN(CTR, MVL)`.
 In combination with SVP64 [[sv/branches]] this can save one instruction
-inside critical inner loops. Note: to avoid having an extra bit in `setvl`,
+inside critical inner loops. Note: to avoid having an extra opcode
+bit in `setvl`,
 to select CTR is slightly convoluted.
 
 # Format