From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 03:00:26 +0000 (-0800)
Subject: Remove extraneous synth_xilinx call
X-Git-Tag: working-ls180~921^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0ee4cd88f1f966c194fdc60e47ef67944882afb;p=yosys.git

Remove extraneous synth_xilinx call
---

diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index 36367eff1..a2ede75a5 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -62,7 +62,6 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w3r
 proc
 memory -nomap
-synth_xilinx
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 memory
 opt -full
@@ -83,7 +82,6 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w3r -chparam A_WIDTH 6
 proc
 memory -nomap
-synth_xilinx
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 memory
 opt -full