From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 30 Sep 2020 09:30:41 +0000 (+0100)
Subject: comb on wr_index not sync
X-Git-Tag: 24jan2021_ls180~272
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d0f4a6e0dc1a10d4a7c22a02634212995df6edae;p=soc.git

comb on wr_index not sync
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 2b230fba..c866f024 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -671,7 +671,7 @@ class ICache(Elaboratable):
         m_in = self.m_in
 
         wr_index = Signal(TLB_SIZE)
-        sync += wr_index.eq(hash_ea(m_in.addr))
+        comb += wr_index.eq(hash_ea(m_in.addr))
 
         with m.If(m_in.tlbie & m_in.doall):
             # Clear all valid bits